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authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>2009-02-20 10:19:19 +0100
committerWolfgang Denk <wd@denx.de>2009-03-20 22:39:14 +0100
commitbb57ad4be76d0e2e7f9ec56678235cc9872ff40f (patch)
treed02d3c5da773f66005bd4c2151e40529d06d4c4a /board/esd/common/fpga.c
parent049216f045fd8e0f45bcef121c2bb1c7d3de6988 (diff)
ppc4xx: Use correct io accessors for esd 405/440 boards
This patch replaces in/out8/16/32 macros by in/out_8/_be16/_be32 macros. Also volatile pointer references are replaced by the new accessors. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/common/fpga.c')
-rw-r--r--board/esd/common/fpga.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
index 5232dddc9e..62c324386c 100644
--- a/board/esd/common/fpga.c
+++ b/board/esd/common/fpga.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
/* ------------------------------------------------------------------------- */
@@ -55,7 +56,7 @@
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
#ifndef SET_FPGA
-# define SET_FPGA(data) out32(GPIO0_OR, data)
+# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data)
#endif
#ifdef FPGA_PROG_ACTIVE_HIGH
@@ -85,10 +86,10 @@
SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
#ifndef FPGA_DONE_STATE
-# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE)
+# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
#endif
#ifndef FPGA_INIT_STATE
-# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT)
+# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
#endif
@@ -139,8 +140,11 @@ static int fpga_boot (const unsigned char *fpgadata, int size)
* Setup port pins for fpga programming
*/
#ifndef CONFIG_M5249
- out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
+ out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ /* setup for output */
+ out_be32 ((void *)GPIO0_TCR,
+ in_be32 ((void *)GPIO0_TCR) |
+ FPGA_PRG | FPGA_CLK | FPGA_DATA);
#endif
SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */