CHROMIUMOS: Add U-boot support for wear-leveling the MRC data

- Depends on related Coreboot changes
- There is a 64k region allocated so use it all
- Write each data blob in a 4K aligned container
- Find the last entry in the region to compare against coreboot copy
- Detect a full region and erase it all and start over at zero

BUG=chrome-os-partner:6962
TEST=manual

I started writing an autotest for this, but it was taking more time
than just doing a thorough manual test.  I will finish the autotest
but for now I relied on manual testing and using /sys/firmware/log
to tell what happened in Coreboot/U-boot on each boot.

TEST CASE 1 - newly flashed image:
1) Install the new bios with flashrom and reboot
2) Check that no MRC data was found by Coreboot in firmware log:
   "prepare_mrc_cache: invalid MRC data"
3) Check that U-boot wrote training data in firmware log:
   "handle_mrc_cache: cached storage mismatch (-1/2895)"
   "firmware_storage_spi: before adjustment"
   "firmware_storage_spi: offset: 0x1ec000"
   "firmware_storage_spi: length: 0xb58"
   "firmware_storage_spi: after adjustment"
   "firmware_storage_spi: offset: 0x1ec000"
   "firmware_storage_spi: length: 0x1000"
   "firmware_storage_spi: offset:          0x001ec000"
   "firmware_storage_spi: adjusted offset: 0x001ec000"
4) Check the flash to see if it has data in first slot
   > flashrom -r /tmp/bios.now
   > hexdump -Cv -s $((0x1ec000)) -n $((0x10000)) /tmp/bios.now

TEST CASE 2 - ensure that it uses the saved training data:
1) Reboot
2) Check that Coreboot used the training data in firmware log:
   "prepare_mrc_cache: at ff9ec009, entry 0 size b4f checksum 9c"
3) Check that U-boot did not have to update the data in firmware log:
   "handle_mrc_cache: cached storage match"
4) Check the flash to see if it still only has data in first slot:
   > flashrom -r /tmp/bios.now
   > hexdump -Cv -s $((0x1ec000)) -n $((0x10000)) /tmp/bios.now

TEST CASE 3 - ensure that it fills the next slot with new data:
1) Corrupt the seed checksum in CMOS:
   > io_write8 0x70 0x78
   > io_write8 0x71 0x00
2) Reboot
3) Check that Coreboot did not use cached data in firmware log:
   "prepare_mrc_cache: invalid seed checksum"
4) Check that U-boot wrote new training data at new offset in firmware log:
   "handle_mrc_cache: cached storage mismatch (2895/2895)"
   "firmware_storage_spi: before adjustment"
   "firmware_storage_spi: offset: 0x1ed000"
   "firmware_storage_spi: length: 0xb58"
   "firmware_storage_spi: after adjustment"
   "firmware_storage_spi: offset: 0x1ed000"
   "firmware_storage_spi: length: 0x1000"
   "firmware_storage_spi: offset:          0x001ed000"
   "firmware_storage_spi: adjusted offset: 0x001ed000"

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifffce29c5f9324f110c047a44a3f66d2e21cd6a4
Reviewed-on: https://gerrit.chromium.org/gerrit/13589
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>

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