Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (145 commits)
  beagleboard: enable HUB power on all variants of the BeagleBoard
  dm3730: enable dpll5
  ehci-hcd: Allow cleanups to happen gracefully on a timeout.
  OMAP3: Add DSS driver for OMAP3
  led: Remove state-saving of led for toggle functionality and add toggle option to led command
  led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all'
  led: correct off/on locations in structure
  led: added cmd_led to Makefile
  BeagleBoard: fix LED 0/1 in driver
  Corrected LED name match finding avoiding extraneous Usage printouts
  BeagleBoard: config: updated default configuration
  BeagleBoard: config: Enabled multibus support for I2C in configuration
  BeagleBoard: config: add optargs/buddy/camera
  BeagleBoard: config: increase command-line functionality
  BeagleBoard: config: make mtest run
  BeagleBoard: config: enable DSS
  BeagleBoard: config: enable asix driver and dhcp
  BeagleBoard: config: enable networking
  BeagleBoard: config: decrease bootdelay to 2 seconds
  BeagleBoard: config: use uImage.beagle for tftp
  BeagleBoard: config: hardcode MAC for onboard SMSC
  BeagleBoard: config: load kernel from MMC ext, not FAT
  BeagleBoard: Configure DVI/S-video
  BeagleBoard: Added userbutton command
  BeagleBoard: turn off clocks in ehci_stop
  USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor
  beagleboard: add support for xM revision C
  beagle: pass expansionboard name in bootargs
  OMAP: Remove omapfb.debug=y from Beagle and Overo env settings
  OMAP3 Beagle Pin Mux initialization glitch fix
  da850: modifications for Logic PD Rev.3 AM18xx EVM
  da850: fix the channel number for EMAC teardown init
  da850: add support for Spectrum Digital AM18xx EVM
  da850: add support to wake up DSP during board init
  da850: modify the U-Boot prompt string
  da850: add NOR boot mode support
  da8xx: add support for multiple PLL controllers
  da850: indicate cache usage disable in config file
  dm365: modify boot prompt from dm365 to dm36x
  dm365: disable cache usage due to coherency issues
  dm6446: disable cache usage due to coherency issues
  OMAP3: Remove legacy mmc driver
  devkit8000: Use generic MMC driver
  TI OMAP3 SDP3430: Use generic MMC driver
  AM3517 CraneBoard: Use generic MMC driver
  OMAP3: pandora: Use generic MMC driver
  OMAP3: Zoom2: Use generic MMC driver
  OMAP3: Zoom1: Use generic MMC driver
  OMAP3: DIG297: Use generic MMC driver
  OMAP3: CM-T35: Use generic MMC driver
  am3517evm: Use generic MMC driver
  omap3evm: Use generic MMC driver
  omap3:clock: check cpu_family before enabling clks for IVA & CAM
  omap3:clock: configure GFX clock to 200MHz for AM/DM37x
  OMAP3/4: Increase console I/O buffer size
  PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE
  PXA: Fix CSB226, fix monitor length
  PXA: Fix Lubbock, remove redundant parenthesis
  armv7: cache: remove flush on un-aligned invalidate
  armv7: stronger barrier for cache-maintenance operations
  omap: enable caches at system start-up
  arm: do not force d-cache enable on all boards
  ORIGEN: Add MMC SPL support
  ARMV7: Add support for Samsung ORIGEN board
  i2c:gpio:s5p: Enable I2C GPIO on the GONI target
  i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
  Tegra2: Use clock and pinmux functions to simplify code
  Tegra2: Add additional pin multiplexing features
  Tegra2: Add more clock support
  Tegra2: Add microsecond timer function
  ARM: remove broken "at91rm9200dk" board
  ARM: remove broken "m501sk" board
  ARM: remove broken "kb9202" board
  ARM: remove broken "csb637" board
  ARM: remove broken "cmc_pu2" board
  ARM: remove broken "at91cap9adk" board
  ARM: remove broken "voiceblue" board
  ARM: remove broken "smdk2400" board
  ARM: remove broken "sbc2410x" board
  ARM: remove broken "netstar" board
  ARM: remove broken "mx1fs2" board
  ARM: remove broken "lpd7a40x" boards
  ARM: remove broken "edb93xx" boards
  ARM: remove broken "B2" board
  ARM: remove broken "armadillo" board
  ARM: remove broken "assabet" board
  ARM: versatile: drop warnings
  IMX: scb9328: drop warnings
  MX31: imx31_litekit: make use of GPIO framework
  MX31: mx31ads: make use of GPIO framework
  MX5: mx51evk: make use of GPIO framework
  MX35: mx35pdk: make use of GPIO framework
  MX5: mx53loco: make use of GPIO framework
  MX5: mx53evk: make use of GPIO framework
  MX5: vision2: make use of GPIO framework
  MX5: mx53smd: make use of GPIO framework
  MX5: mx53ard: make use of GPIO framework
  MX25: zmx25: make use of GPIO framework
  MX5: efikamx: make use of GPIO framework
  MX31: QONG: make use of GPIO framework
  MX35: make use of GPIO framework for MX35 processor
  MX5: make use of GPIO framework for MX5 processor
  MX31: make use of GPIO framework for MX31 processor
  MX25: make use of GPIO framework for MX25 processor
  IMX: uniform GPIO interface using GPIO framework
  MX: MX35 / MX5: uniform clock command with powerpc
  MX35: MX35PDK: support additional RAM on CSD1
  mx53: ddr3: Update DD3 initialization
  ARM: MX51: PLL errata workaround
  ARM: versatilepb : drop warnings due to double definitions
  omap4: increase SRAM budget to fix build error
  omap4: fix build warning due to signed unsigned comparison
  mkimage: Fix 'Unknown OMAP image type - 5'
  omap: fix gpio related build breaks
  gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal)
  SMDKV310: MMC SPL: Remove unwanted dummy functions
  SMDKV310: Fix undefined reference error
  SMDKV310: Fix build error for smdkv310 board
  gpio:samsung s5p_ suffix add for GPIO functions
  mmc: S5P: Support DMA restarts at buffer boundaries
  SMDKV310: Fix host compilation of mkv310_image
  arm: fix bd pointer dereference prior initialization
  arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize
  mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
  MX31: removed warnings due to clock.h
  integrator: convert to new build system
  integratorcp: make the board compile
  integratorap: remove hardcoded 32MB memory cmdline
  ...

1 files changed, 0 insertions, 167 deletions

diff --git a/board/dave/B2/lowlevel_init.S b/board/dave/B2/lowlevel_init.S
deleted file mode 100644
index 2f3a3645ed6..00000000000
--- a/board/dave/B2/lowlevel_init.S
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
- * Modified By MATTO
- *
- * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-/*
- * Documentation:
- * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
- *     Advanced Developer's manual, December 1999
- *
- * Intel has a very hard to find SDRAM configurator on their web site:
- *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
- *
- * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
- * appears to be true, but it might be possible that somebody designs a
- * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
- *
- * 04-10-2001:  SELETZ
- * - separated memory config for multiple platform support
- * - perform SA1110 Hardware Reset Procedure
- *
- */
-
-.equ    B0_Tacs,      0x0 /* 0clk */
-.equ    B0_Tcos,      0x0 /* 0clk */
-.equ    B0_Tacc,      0x4 /* 6clk */
-.equ    B0_Tcoh,      0x0 /* 0clk */
-.equ    B0_Tah,       0x0 /* 0clk */
-.equ    B0_Tacp,      0x0 /* 0clk */
-.equ    B0_PMC,       0x0 /* normal(1data) */
-/* Bank 1 parameter */
-.equ    B1_Tacs,      0x3 /* 4clk */
-.equ    B1_Tcos,      0x3 /* 4clk */
-.equ    B1_Tacc,      0x7 /* 14clkv */
-.equ    B1_Tcoh,      0x3 /* 4clk */
-.equ    B1_Tah,       0x3 /* 4clk */
-.equ    B1_Tacp,      0x3 /* 6clk */
-.equ    B1_PMC,       0x0 /* normal(1data) */
-
-/* Bank 2 parameter - LAN91C96 */
-.equ    B2_Tacs,      0x3 /* 4clk */
-.equ    B2_Tcos,      0x3 /* 4clk */
-.equ    B2_Tacc,      0x7 /* 14clk */
-.equ    B2_Tcoh,      0x3 /* 4clk */
-.equ    B2_Tah,       0x3 /* 4clk */
-.equ    B2_Tacp,      0x3 /* 6clk */
-.equ    B2_PMC,       0x0 /* normal(1data) */
-
-/* Bank 3 parameter */
-.equ    B3_Tacs,      0x3 /* 4clk */
-.equ    B3_Tcos,      0x3 /* 4clk */
-.equ    B3_Tacc,      0x7 /* 14clk */
-.equ    B3_Tcoh,      0x3 /* 4clk */
-.equ    B3_Tah,       0x3 /* 4clk */
-.equ    B3_Tacp,      0x3 /* 6clk */
-.equ    B3_PMC,       0x0 /* normal(1data) */
-
-/* Bank 4 parameter */
-.equ    B4_Tacs,      0x3 /* 4clk */
-.equ    B4_Tcos,      0x3 /* 4clk */
-.equ    B4_Tacc,      0x7 /* 14clk */
-.equ    B4_Tcoh,      0x3 /* 4clk */
-.equ    B4_Tah,       0x3 /* 4clk */
-.equ    B4_Tacp,      0x3 /* 6clk */
-.equ    B4_PMC,       0x0 /* normal(1data) */
-
-/* Bank 5 parameter */
-.equ    B5_Tacs,      0x3 /* 4clk */
-.equ    B5_Tcos,      0x3 /* 4clk */
-.equ    B5_Tacc,      0x7 /* 14clk */
-.equ    B5_Tcoh,      0x3 /* 4clk */
-.equ    B5_Tah,       0x3 /* 4clk */
-.equ    B5_Tacp,      0x3 /* 6clk */
-.equ    B5_PMC,       0x0 /* normal(1data) */
-
-/* Bank 6(if SROM) parameter */
-.equ    B6_Tacs,      0x3 /* 4clk */
-.equ    B6_Tcos,      0x3 /* 4clk */
-.equ    B6_Tacc,      0x7 /* 14clk */
-.equ    B6_Tcoh,      0x3 /* 4clk */
-.equ    B6_Tah,       0x3 /* 4clk */
-.equ    B6_Tacp,      0x3 /* 6clk */
-.equ    B6_PMC,       0x0 /* normal(1data) */
-
-/* Bank 7(if SROM) parameter */
-.equ    B7_Tacs,      0x3 /* 4clk */
-.equ    B7_Tcos,      0x3 /* 4clk */
-.equ    B7_Tacc,      0x7 /* 14clk */
-.equ    B7_Tcoh,      0x3 /* 4clk */
-.equ    B7_Tah,       0x3 /* 4clk */
-.equ    B7_Tacp,      0x3 /* 6clk */
-.equ    B7_PMC,       0x0 /* normal(1data) */
-
-/* Bank 6 parameter */
-.equ    B6_MT,        0x3 /* SDRAM */
-.equ    B6_Trcd,      0x0 /* 2clk */
-.equ    B6_SCAN,      0x0 /* 10bit */
-
-.equ    B7_MT,        0x3 /* SDRAM */
-.equ    B7_Trcd,      0x0 /* 2clk */
-.equ    B7_SCAN,      0x0 /* 10bit */
-
-
-/* REFRESH parameter */
-.equ    REFEN,        0x1 /* Refresh enable */
-.equ    TREFMD,       0x0 /* CBR(CAS before RAS)/Auto refresh */
-.equ    Trp,        0x0 /* 2clk */
-.equ    Trc,        0x3 /* 0x1=5clk 0x3=11clk*/
-.equ    Tchr,       0x0 /* 0x2=3clk 0x0=0clks  */
-.equ    REFCNT,       879
-
-MEMORY_CONFIG:
-  .long   0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
-  .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
-  .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
-  .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
-  .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
-  .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
-  .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
-  .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  /*GCS6*/
-  .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  /*GCS7*/
-  .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
-  .word 0x17      /*SCLK power down mode, BANKSIZE 16M/16M*/
-  .word 0x20      /*MRSR6 CL=2clk*/
-  .word 0x20      /*MRSR7*/
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/*
-		the next instruction fail due memory relocation...
-		we'll find the right MEMORY_CONFIG address with the next 3 lines...
-	*/
-	/*ldr r0, =MEMORY_CONFIG*/
-	mov r0, pc
-	ldr r1, =(0x38+4)
-	sub r0, r0, r1
-
-	ldmia r0, {r1-r13}
-	ldr   r0, =0x01c80000
-	stmia r0, {r1-r13}
-	mov pc, lr