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authorwdenk <wdenk>2005-04-03 23:35:57 +0000
committerwdenk <wdenk>2005-04-03 23:35:57 +0000
commit50712ba16e7e469e90952a7f197efa46e2f8e311 (patch)
tree4a6bf30c2ba3af8be123938f236eadca28c964d5 /board/csb472/init.S
parent901787d6e83b6a5beba5905fbc5441673dcd63e1 (diff)
* Patch by Mathias Küster, 23 Nov 2004:
add udelay support for the mcf5282 cpu * Patch by Tolunay Orkun, 16 November 2004: fix incorrect onboard Xilinx CPLD base address
Diffstat (limited to 'board/csb472/init.S')
-rw-r--r--board/csb472/init.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/csb472/init.S b/board/csb472/init.S
index ca0241bd8a2..aec42a14b97 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -129,7 +129,7 @@ ext_bus_cntlr_init:
*******************************************************************/
/*WDCR_EBC(pb3ap, 0x07869200)*/
WDCR_EBC(pb3ap, 0x04055200)
- WDCR_EBC(pb3cr, 0xff01c000)
+ WDCR_EBC(pb3cr, 0xf081c000)
/********************************************************************
* Memory Bank 1,2,4-7 (Unused) initialization
*******************************************************************/