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authorStefan Roese <sr@denx.de>2009-09-24 13:59:57 +0200
committerStefan Roese <sr@denx.de>2009-09-28 10:45:54 +0200
commit95b602bab5fec2fffab07a01ea3947c70d1bacc1 (patch)
treeacee523787d213090cc592029f1d566473bc1fd7 /board/csb272
parent952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (diff)
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/csb272')
-rw-r--r--board/csb272/csb272.c8
-rw-r--r--board/csb272/init.S18
2 files changed, 13 insertions, 13 deletions
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 740e3ac6f5e..d6d65cf45cf 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -135,28 +135,28 @@ phys_size_t initdram (int board_type)
tot_size = 0;
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
diff --git a/board/csb272/init.S b/board/csb272/init.S
index 15b26f8bf86..a6b0d4045a7 100644
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -175,26 +175,26 @@ sdram_init:
* Disable memory controller to allow
* values to be changed.
*/
- WDCR_SDRAM(mem_mcopt1, 0x00000000)
+ WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/*
* Configure Memory Banks
*/
- WDCR_SDRAM(mem_mb0cf, 0x00084001)
- WDCR_SDRAM(mem_mb1cf, 0x00000000)
- WDCR_SDRAM(mem_mb2cf, 0x00000000)
- WDCR_SDRAM(mem_mb3cf, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
+ WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/*
* Set up SDTR1 (SDRAM Timing Register)
*/
- WDCR_SDRAM(mem_sdtr1, 0x00854009)
+ WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/*
* Set RTR (Refresh Timing Register)
*/
- WDCR_SDRAM(mem_rtr, 0x10000000)
- /* WDCR_SDRAM(mem_rtr, 0x05f00000) */
+ WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
+ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst
@@ -210,7 +210,7 @@ sdram_init:
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
- WDCR_SDRAM(mem_mcopt1,0x80800000)
+ WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done:
blr /* Return to calling function */