diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2011-09-12 15:52:06 -0700 |
---|---|---|
committer | Vincent Palatin <vpalatin@chromium.org> | 2011-09-12 17:51:10 -0700 |
commit | 1c9d94fd0e6c1d6f8a6592fc653ed2c14252a1eb (patch) | |
tree | cdc6fd145ea58cfd4da57e590c4f348c8b1e05eb /board/chromebook-x86 | |
parent | 099ece097185328f6c8c1532545d251960005406 (diff) |
declare 1-to-1 mapping for PCI bus address space
On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly.
This fixes the EHCI PCI driver initialization on Stumpy.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:5752
TEST=on stumpy board, use "usb start" on U-Boot command line and check
we can detect USB-ethernet devices and USB mass storage devices.
Change-Id: Ie3da48d14b0b7dec5a156c009f5c4f72cd337aa5
Reviewed-on: http://gerrit.chromium.org/gerrit/7570
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'board/chromebook-x86')
-rw-r--r-- | board/chromebook-x86/coreboot/coreboot_pci.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/chromebook-x86/coreboot/coreboot_pci.c index f0fa1b2d348..c9893505d4b 100644 --- a/board/chromebook-x86/coreboot/coreboot_pci.c +++ b/board/chromebook-x86/coreboot/coreboot_pci.c @@ -55,7 +55,10 @@ void pci_init_board(void) coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; coreboot_hose.last_busno = 0; - coreboot_hose.region_count = 0; + + pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + coreboot_hose.region_count = 1; pci_setup_type1(&coreboot_hose, X86_PCI_CONFIG_ADDR, X86_PCI_CONFIG_DATA); |