CHROMIUMOS: x86: Fix MTRR clear to detect which MTRR to use

Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

BUG=chrome-os-partner:7350
TEST=boot 4GB stumpy with coreboot MTRR fixes and verify
that U-boot does not clear MTRR 7 but does clear MTRR 9.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id6927325131b0b88043daa320a17847764626c0d
Reviewed-on: https://gerrit.chromium.org/gerrit/13477
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>

1 files changed, 15 insertions, 4 deletions

diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c
index 8574dad4ca..ac4fae9531 100644
--- a/board/chromebook-x86/coreboot/coreboot.c
+++ b/board/chromebook-x86/coreboot/coreboot.c
@@ -211,6 +211,8 @@ int board_use_usb_keyboard(int boot_mode)
 	return 0;
 }
 
+#define MTRR_TYPE_WP          5
+#define MTRRcap_MSR           0xfe
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
@@ -218,11 +220,20 @@ int board_final_cleanup(void)
 {
 	/* Un-cache the ROM so the kernel has one
 	 * more MTRR available.
+	 *
+	 * Coreboot should have assigned this to the
+	 * top available variable MTRR.
 	 */
-	disable_cache();
-	wrmsr(MTRRphysBase_MSR(7), 0);
-	wrmsr(MTRRphysMask_MSR(7), 0);
-	enable_cache();
+	u8 top_mtrr = (rdmsr(MTRRcap_MSR) & 0xff) - 1;
+	u8 top_type = rdmsr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+
+	/* Make sure this MTRR is the correct Write-Protected type */
+	if (top_type == MTRR_TYPE_WP) {
+		disable_cache();
+		wrmsr(MTRRphysBase_MSR(top_mtrr), 0);
+		wrmsr(MTRRphysMask_MSR(top_mtrr), 0);
+		enable_cache();
+	}
 
 	return 0;
 }