diff options
| author | Gabe Black <gabeblack@google.com> | 2011-06-14 14:28:46 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:39:25 -0700 |
| commit | 36483023bfc0f5f957da787652812b1acb7d6a66 (patch) | |
| tree | f57ed96592afc8cff45f8d77bae6b598e29dcb8d /board/chromebook-x86/coreboot/coreboot_pci.c | |
| parent | f7c9216101e032b2918e0d0afb7564d13290325d (diff) | |
Implement recursively scanning PCI busses on the coreboot "board".
A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.
BUG=chrome-os-partner:4511
TEST=Built coreboot u-boot, ran the PCI command on Alex, saw devices on bus 0,
the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.
Change-Id: I70287594aad2e3abae164db9d2293437a870c00b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://gerrit.chromium.org/gerrit/2604
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Diffstat (limited to 'board/chromebook-x86/coreboot/coreboot_pci.c')
| -rw-r--r-- | board/chromebook-x86/coreboot/coreboot_pci.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/chromebook-x86/coreboot/coreboot_pci.c index f5490ac165..f0fa1b2d34 100644 --- a/board/chromebook-x86/coreboot/coreboot_pci.c +++ b/board/chromebook-x86/coreboot/coreboot_pci.c @@ -25,6 +25,7 @@ * MA 02111-1307 USA */ +#include <common.h> #include <pci.h> #include <asm/pci.h> @@ -33,10 +34,27 @@ static struct pci_controller coreboot_hose; #define X86_PCI_CONFIG_ADDR 0xCF8 #define X86_PCI_CONFIG_DATA 0xCFC +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + hose->last_busno = max(hose->last_busno, secondary); + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_coreboot_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge}, + {} +}; + void pci_init_board(void) { + coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0xff; + coreboot_hose.last_busno = 0; coreboot_hose.region_count = 0; pci_setup_type1(&coreboot_hose, X86_PCI_CONFIG_ADDR, @@ -44,5 +62,5 @@ void pci_init_board(void) pci_register_hose(&coreboot_hose); - coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); + pci_hose_scan(&coreboot_hose); } |