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authorPeter Chubb <Peter.Chubb@data61.csiro.au>2016-08-30 22:54:46 +0000
committerTom Warren <twarren@nvidia.com>2016-09-01 09:24:30 -0700
commitb615267633996a9410a88b54a55965d8b021f6f8 (patch)
tree2a3e8377ac5ef72bbc1fae56da520513c0971891 /board/cei/cei-tk1-som/cei-tk1-som.c
parent7932d3e4a7d23c8b9b9ecd50f1869eaf3e46ed49 (diff)
ARM: tegra: Add support for TK1-SOM board from Colorado Engineering
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'board/cei/cei-tk1-som/cei-tk1-som.c')
-rw-r--r--board/cei/cei-tk1-som/cei-tk1-som.c65
1 files changed, 65 insertions, 0 deletions
diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c
new file mode 100644
index 0000000000..9ba7490c38
--- /dev/null
+++ b/board/cei/cei-tk1-som/cei-tk1-som.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <power/as3722.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+
+#include "pinmux-config-cei-tk1-som.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_clear_tristate_input_clamping();
+
+ gpio_config_table(cei_tk1_som_gpio_inits,
+ ARRAY_SIZE(cei_tk1_som_gpio_inits));
+
+ pinmux_config_pingrp_table(cei_tk1_som_pingrps,
+ ARRAY_SIZE(cei_tk1_som_pingrps));
+
+ pinmux_config_drvgrp_table(cei_tk1_som_drvgrps,
+ ARRAY_SIZE(cei_tk1_som_drvgrps));
+
+ pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps,
+ ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *pmic;
+ int err;
+
+ err = as3722_init(&pmic);
+ if (err) {
+ error("failed to initialize AS3722 PMIC: %d\n", err);
+ return err;
+ }
+
+ err = as3722_sd_enable(pmic, 4);
+ if (err < 0) {
+ error("failed to enable SD4: %d\n", err);
+ return err;
+ }
+
+ err = as3722_sd_set_voltage(pmic, 4, 0x24);
+ if (err < 0) {
+ error("failed to set SD4 voltage: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+#endif /* PCI */