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authorStefan Roese <sr@denx.de>2007-11-30 07:15:41 +0100
committerStefan Roese <sr@denx.de>2007-11-30 07:15:41 +0100
commite15e33433e7c05111968dc9b434a52fd42cbd221 (patch)
treebdf6f2bf2221dd49c2f60f042af471fe550c7680 /board/amcc
parent8be760903645af09871be50ad0a6f9ebb62b311d (diff)
ppc4xx: Kilauea: Add PCIe reset assertion upon power-up
This manual PCIe reset triggering solves the problem seen with the Intel EPRO/1000 card, which was not detected (link not established) upon power-up reset. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc')
-rw-r--r--board/amcc/kilauea/kilauea.c15
1 files changed, 6 insertions, 9 deletions
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 09b7382c4ef..36e9e4a2117 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -37,14 +37,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-void fpga_init(void)
-{
- /*
- * Set FPGA regs
- */
- out32(CFG_FPGA_BASE, 0xff570cc0);
-}
-
/*
* Board early initialization function
*/
@@ -199,7 +191,12 @@ int board_early_init_f (void)
*/
mtsdr(SDR0_SRST, 0);
- fpga_init();
+ /*
+ * Configure FPGA register with PCIe reset
+ */
+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
+ mdelay(50);
+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
/* Configure 405EX for NAND usage */
val = SDR0_CUST0_MUX_NDFC_SEL |