diff options
author | Stefan Roese <sr@denx.de> | 2009-09-09 16:25:29 +0200 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2009-09-11 10:35:58 +0200 |
commit | d1c3b27525b664e8c4db6bb173eed51bfc8220de (patch) | |
tree | c00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/amcc/taishan | |
parent | e7963772eb78a6aa1fa65063d64eab3a8626daac (diff) |
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/taishan')
-rw-r--r-- | board/amcc/taishan/showinfo.c | 70 | ||||
-rw-r--r-- | board/amcc/taishan/taishan.c | 44 |
2 files changed, 57 insertions, 57 deletions
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 2a78a22e65e..e4e441b319d 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -33,60 +33,60 @@ void show_reset_reg(void) /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); - mfcpr(clk_pllc,reg); + mfcpr(CPR0_PLLC,reg); printf("cpr_pllc = %#010lx\n",reg); - mfcpr(clk_plld,reg); + mfcpr(CPR0_PLLD,reg); printf("cpr_plld = %#010lx\n",reg); - mfcpr(clk_primad,reg); + mfcpr(CPR0_PRIMAD,reg); printf("cpr_primad = %#010lx\n",reg); - mfcpr(clk_primbd,reg); + mfcpr(CPR0_PRIMBD,reg); printf("cpr_primbd = %#010lx\n",reg); - mfcpr(clk_opbd,reg); + mfcpr(CPR0_OPBD,reg); printf("cpr_opbd = %#010lx\n",reg); - mfcpr(clk_perd,reg); + mfcpr(CPR0_PERD,reg); printf("cpr_perd = %#010lx\n",reg); - mfcpr(clk_mald,reg); + mfcpr(CPR0_MALD,reg); printf("cpr_mald = %#010lx\n",reg); /* read sdr register */ - mfsdr(sdr_ebc,reg); - printf("sdr_ebc = %#010lx\n",reg); + mfsdr(SDR0_EBC,reg); + printf("SDR0_EBC = %#010lx\n",reg); - mfsdr(sdr_cp440,reg); - printf("sdr_cp440 = %#010lx\n",reg); + mfsdr(SDR0_CP440,reg); + printf("SDR0_CP440 = %#010lx\n",reg); - mfsdr(sdr_xcr,reg); - printf("sdr_xcr = %#010lx\n",reg); + mfsdr(SDR0_XCR,reg); + printf("SDR0_XCR = %#010lx\n",reg); - mfsdr(sdr_xpllc,reg); - printf("sdr_xpllc = %#010lx\n",reg); + mfsdr(SDR0_XPLLC,reg); + printf("SDR0_XPLLC = %#010lx\n",reg); - mfsdr(sdr_xplld,reg); - printf("sdr_xplld = %#010lx\n",reg); + mfsdr(SDR0_XPLLD,reg); + printf("SDR0_XPLLD = %#010lx\n",reg); - mfsdr(sdr_pfc0,reg); - printf("sdr_pfc0 = %#010lx\n",reg); + mfsdr(SDR0_PFC0,reg); + printf("SDR0_PFC0 = %#010lx\n",reg); - mfsdr(sdr_pfc1,reg); - printf("sdr_pfc1 = %#010lx\n",reg); + mfsdr(SDR0_PFC1,reg); + printf("SDR0_PFC1 = %#010lx\n",reg); - mfsdr(sdr_cust0,reg); - printf("sdr_cust0 = %#010lx\n",reg); + mfsdr(SDR0_CUST0,reg); + printf("SDR0_CUST0 = %#010lx\n",reg); - mfsdr(sdr_cust1,reg); - printf("sdr_cust1 = %#010lx\n",reg); + mfsdr(SDR0_CUST1,reg); + printf("SDR0_CUST1 = %#010lx\n",reg); - mfsdr(sdr_uart0,reg); - printf("sdr_uart0 = %#010lx\n",reg); + mfsdr(SDR0_UART0,reg); + printf("SDR0_UART0 = %#010lx\n",reg); - mfsdr(sdr_uart1,reg); - printf("sdr_uart1 = %#010lx\n",reg); + mfsdr(SDR0_UART1,reg); + printf("SDR0_UART1 = %#010lx\n",reg); printf("===== Display reset and initialize register End =========\n"); } @@ -96,14 +96,14 @@ void show_xbridge_info(void) unsigned long reg; printf("PCI-X chip control registers\n"); - mfsdr(sdr_xcr, reg); - printf("sdr_xcr = %#010lx\n", reg); + mfsdr(SDR0_XCR, reg); + printf("SDR0_XCR = %#010lx\n", reg); - mfsdr(sdr_xpllc, reg); - printf("sdr_xpllc = %#010lx\n", reg); + mfsdr(SDR0_XPLLC, reg); + printf("SDR0_XPLLC = %#010lx\n", reg); - mfsdr(sdr_xplld, reg); - printf("sdr_xplld = %#010lx\n", reg); + mfsdr(SDR0_XPLLD, reg); + printf("SDR0_XPLLD = %#010lx\n", reg); printf("PCI-X Bridge Configure registers\n"); printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID)); diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 53ce88c6cdf..086778a6523 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -47,7 +47,7 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT | @@ -56,66 +56,66 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | 64MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | + mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | + mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | LCM. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | TMP. Initialize bank 3 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | + mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | Connector 4~7. Initialize bank 3~ 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb4ap,0); - mtebc(pb4cr,0); - mtebc(pb5ap,0); - mtebc(pb5cr,0); - mtebc(pb6ap,0); - mtebc(pb6cr,0); - mtebc(pb7ap,0); - mtebc(pb7cr,0); + mtebc(PB4AP,0); + mtebc(PB4CR,0); + mtebc(PB5AP,0); + mtebc(PB5CR,0); + mtebc(PB6AP,0); + mtebc(PB6CR,0); + mtebc(PB7AP,0); + mtebc(PB7CR,0); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -164,13 +164,13 @@ int board_early_init_f (void) mtdcr (uic0vr, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ - mfsdr(sdr_pfc0,reg); + mfsdr(SDR0_PFC0,reg); reg |= 0x00300000; - mtsdr(sdr_pfc0,reg); + mtsdr(SDR0_PFC0,reg); - mfsdr(sdr_pfc1,reg); + mfsdr(SDR0_PFC1,reg); reg |= 0x00100000; - mtsdr(sdr_pfc1,reg); + mtsdr(SDR0_PFC1,reg); /* Set GPIO 10 and 11 as output */ GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718); @@ -230,7 +230,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; |