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authorMarek Vasut <marex@denx.de>2015-08-01 21:35:18 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:27 +0200
commit5af914189ec73b2241ba79950f98849fddaf32a2 (patch)
tree7fb001c10390c637f203ffde607c4ef458653e7f /board/altera
parent99f453e9533f590fe40432b62c131625d7e91e46 (diff)
ddr: altera: sdram: Introduce socfpga_sdram_get_config()
Introduce socfpga_sdram_get_config() function implement in a board file, which returns the socfpga_sdram_config structure. This is the last step in cleaning up the socfpga_mmr_init_full(), but not the last step which allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c thus far. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/altera')
-rw-r--r--board/altera/socfpga/Makefile3
-rw-r--r--board/altera/socfpga/wrap_sdram_config.c185
2 files changed, 187 insertions, 1 deletions
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index 640f6298567..5a15c716106 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -7,4 +7,5 @@
#
obj-y := socfpga.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o
+obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
+ wrap_sdram_config.o
diff --git a/board/altera/socfpga/wrap_sdram_config.c b/board/altera/socfpga/wrap_sdram_config.c
new file mode 100644
index 00000000000..c70854e6e38
--- /dev/null
+++ b/board/altera/socfpga/wrap_sdram_config.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/sdram.h>
+/* QTS output file. */
+#include "qts/sdram_config.h"
+
+static const struct socfpga_sdram_config sdram_config = {
+ .ctrl_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+ SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
+ .dram_timing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
+ .dram_timing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
+ .dram_timing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
+ .dram_timing4 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
+ .lowpwr_timing =
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
+ .dram_odt =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+ SDR_CTRLGRP_DRAMODT_READ_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+ SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+ .dram_addrw =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
+ ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
+ .dram_if_width =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+ SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
+ .dram_dev_width =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+ SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
+ .dram_intr =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+ SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
+ .lowpwr_eq =
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+ SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
+ .static_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
+ .ctrl_width =
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+ SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
+ .cport_width =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+ SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
+ .cport_wmap =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+ SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
+ .cport_rmap =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+ SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
+ .rfifo_cmap =
+ (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+ SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
+ .wfifo_cmap =
+ (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+ SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
+ .cport_rdwr =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+ SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
+ .port_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+ SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
+ .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+ .fifo_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
+ .mp_priority =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+ SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
+ .mp_weight0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
+ .mp_weight1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
+ .mp_weight2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
+ .mp_weight3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
+ .mp_pacing0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
+ .mp_pacing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
+ .mp_pacing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
+ .mp_pacing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
+ .mp_threshold0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
+ .mp_threshold1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
+ .mp_threshold2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
+ .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+};
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
+{
+ return &sdram_config;
+}