diff options
| author | Marek Vasut <marex@denx.de> | 2015-08-10 21:24:53 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-23 11:56:19 +0200 |
| commit | f089240128329fe6a49a5272aef732b47613c2f5 (patch) | |
| tree | 40fb3564ff53efcf82d58774547db091e9f4aa6f /board/altera/arria5-socdk/qts/pinmux_config.h | |
| parent | cd9b73177100598e7be0a9033a4a2ed4a7d24fbb (diff) | |
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.
On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/altera/arria5-socdk/qts/pinmux_config.h')
| -rw-r--r-- | board/altera/arria5-socdk/qts/pinmux_config.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/board/altera/arria5-socdk/qts/pinmux_config.h b/board/altera/arria5-socdk/qts/pinmux_config.h new file mode 100644 index 0000000000..21fabb0b2b --- /dev/null +++ b/board/altera/arria5-socdk/qts/pinmux_config.h @@ -0,0 +1,54 @@ +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PINMUX_CONFIG_H_ +#define _PRELOADER_PINMUX_CONFIG_H_ + +/* + * State of enabling for which IP connected out through the muxing. + * Value 1 mean the IP connection is muxed out + */ +#define CONFIG_HPS_EMAC0 (1) +#define CONFIG_HPS_EMAC1 (0) +#define CONFIG_HPS_USB0 (0) +#define CONFIG_HPS_USB1 (1) +#define CONFIG_HPS_NAND (0) +#define CONFIG_HPS_SDMMC (1) +#define CONFIG_HPS_QSPI (0) +#define CONFIG_HPS_UART0 (1) +#define CONFIG_HPS_UART1 (0) +#define CONFIG_HPS_TRACE (0) +#define CONFIG_HPS_I2C0 (1) +#define CONFIG_HPS_I2C1 (0) +#define CONFIG_HPS_I2C2 (0) +#define CONFIG_HPS_I2C3 (0) +#define CONFIG_HPS_SPIM0 (0) +#define CONFIG_HPS_SPIM1 (0) +#define CONFIG_HPS_SPIS0 (0) +#define CONFIG_HPS_SPIS1 (0) +#define CONFIG_HPS_CAN0 (1) +#define CONFIG_HPS_CAN1 (0) + +/* IP attribute value (which affected by pin muxing configuration) */ +#define CONFIG_HPS_SDMMC_BUSWIDTH (8) + +/* 1 if the pins are connected out */ +#define CONFIG_HPS_QSPI_CS0 (0) +#define CONFIG_HPS_QSPI_CS1 (0) +#define CONFIG_HPS_QSPI_CS2 (0) +#define CONFIG_HPS_QSPI_CS3 (0) + +/* UART */ +/* 1 means the pin is mux out or available */ +#define CONFIG_HPS_UART0_TX (1) +#define CONFIG_HPS_UART0_RX (1) +#define CONFIG_HPS_UART0_CTS (0) +#define CONFIG_HPS_UART0_RTS (0) +#define CONFIG_HPS_UART1_TX (0) +#define CONFIG_HPS_UART1_RX (0) +#define CONFIG_HPS_UART1_CTS (0) +#define CONFIG_HPS_UART1_RTS (0) + +/* Pin mux data */ +#define CONFIG_HPS_PINMUX_NUM (207) + +#endif /* _PRELOADER_PINMUX_CONFIG_H_ */ |