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authorChris Packham <judge.packham@gmail.com>2018-06-03 16:21:27 +1200
committerStefan Roese <sr@denx.de>2018-06-05 07:29:09 +0200
commit54e3316ffa46bd81e55216cd5aa5f087e9de9f8f (patch)
treed877199099dd837553dc8676931ee05eb2a7fb4e /board/alliedtelesis
parent87a62bce28a61199f7e51a39ec7f441af5a313cc (diff)
ARM: kirkwood: SBx81LIFKW: Enable network hardware
The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC. For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/alliedtelesis')
-rw-r--r--board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
index 3cacdc8372..e58bbf07ef 100644
--- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
+++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
@@ -164,16 +164,26 @@ int board_init(void)
return 0;
}
-#ifdef CONFIG_MV88E61XX_SWITCH
-/* Configure and enable Switch and PHY */
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
void reset_phy(void)
{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
/* Ensure the 88e6097 gets at least 10ms Reset
*/
kw_gpio_set_value(MV88E6097_RESET, 0);
mdelay(20);
kw_gpio_set_value(MV88E6097_RESET, 1);
mdelay(20);
+
+ phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+ return 0;
}
#endif