diff options
author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
---|---|---|
committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board/Marvell | |
parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board/Marvell')
-rw-r--r-- | board/Marvell/common/bootseq.txt | 2 | ||||
-rw-r--r-- | board/Marvell/common/flash.c | 22 | ||||
-rw-r--r-- | board/Marvell/common/i2c.c | 8 | ||||
-rw-r--r-- | board/Marvell/common/intel_flash.c | 4 | ||||
-rw-r--r-- | board/Marvell/common/intel_flash.h | 2 | ||||
-rw-r--r-- | board/Marvell/common/misc.S | 18 | ||||
-rw-r--r-- | board/Marvell/common/ns16550.c | 6 | ||||
-rw-r--r-- | board/Marvell/common/ns16550.h | 2 | ||||
-rw-r--r-- | board/Marvell/common/serial.c | 22 | ||||
-rw-r--r-- | board/Marvell/db64360/db64360.c | 146 | ||||
-rw-r--r-- | board/Marvell/db64360/mpsc.c | 6 | ||||
-rw-r--r-- | board/Marvell/db64360/pci.c | 26 | ||||
-rw-r--r-- | board/Marvell/db64360/sdram_init.c | 28 | ||||
-rw-r--r-- | board/Marvell/db64360/u-boot.lds | 3 | ||||
-rw-r--r-- | board/Marvell/db64460/db64460.c | 146 | ||||
-rw-r--r-- | board/Marvell/db64460/mpsc.c | 6 | ||||
-rw-r--r-- | board/Marvell/db64460/pci.c | 26 | ||||
-rw-r--r-- | board/Marvell/db64460/sdram_init.c | 28 | ||||
-rw-r--r-- | board/Marvell/db64460/u-boot.lds | 3 |
19 files changed, 259 insertions, 245 deletions
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt index 290aed90a52..e4fefb31dd0 100644 --- a/board/Marvell/common/bootseq.txt +++ b/board/Marvell/common/bootseq.txt @@ -88,7 +88,7 @@ in_flash: nothing mem_malloc_init malloc_bin_reloc - spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) env_relocated misc_init_r(bd): (board/evb64260/evb64260.c) mpsc_init2 diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c index 3603372d076..21eae0e9490 100644 --- a/board/Marvell/common/flash.c +++ b/board/Marvell/common/flash.c @@ -48,7 +48,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last); int write_word_intel (bank_addr_t addr, bank_word_t value); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -68,14 +68,14 @@ unsigned long flash_init (void) unsigned long base, flash_size; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* the boot flash */ - base = CFG_FLASH_BASE; + base = CONFIG_SYS_FLASH_BASE; size_b0 = - flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base, + flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base, &flash_info[0]); printf ("[%ldkB@%lx] ", size_b0 / 1024, base); @@ -84,11 +84,11 @@ unsigned long flash_init (void) printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); } - base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE); + base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE); /* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ - for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { unsigned long size = - flash_get_size (CFG_EXTRA_FLASH_WIDTH, + flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *) base, &flash_info[i]); printf ("[%ldMB@%lx] ", size >> 20, base); @@ -617,7 +617,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* has the timeout limit been reached? */ if (get_timer (start) > - CFG_FLASH_ERASE_TOUT) + CONFIG_SYS_FLASH_ERASE_TOUT) { /* timeout limit reached */ printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); @@ -776,7 +776,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (volatile unsigned char *) (info->start[l_sect]); /* broken for 2x16: TODO */ while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -956,7 +956,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) { /* has the timeout limit been reached? */ if (get_timer (start) > - CFG_FLASH_WRITE_TOUT) { + CONFIG_SYS_FLASH_WRITE_TOUT) { /* timeout limit reached */ printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); /* reset the flash */ @@ -1064,7 +1064,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c index 32b2b30a4a2..d4260443929 100644 --- a/board/Marvell/common/i2c.c +++ b/board/Marvell/common/i2c.c @@ -48,7 +48,7 @@ static void i2c_init (int speed, int slaveaddr) unsigned int actualN = 0, actualM = 0; unsigned int control, status; unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; + unsigned int tclk = CONFIG_SYS_TCLK; unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ DP (puts ("i2c_init\n")); @@ -372,7 +372,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_read\n")); @@ -447,7 +447,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_write\n")); @@ -500,7 +500,7 @@ int i2c_probe (uchar chip) unsigned int i2c_status; #endif uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_probe\n")); diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c index d26f883ad33..42b3ee15486 100644 --- a/board/Marvell/common/intel_flash.c +++ b/board/Marvell/common/intel_flash.c @@ -152,7 +152,7 @@ int write_word_intel (bank_addr_t addr, bank_word_t value) /* data polling for D7 */ start = get_timer (0); do { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { retval = 1; goto done; } @@ -227,7 +227,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last) do { now = get_timer (start); - if (now - estart > CFG_FLASH_ERASE_TOUT) { + if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (sect %d)\n", sect); haderr = 1; break; diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h index 666a4cdcadd..bd8941ea5fc 100644 --- a/board/Marvell/common/intel_flash.h +++ b/board/Marvell/common/intel_flash.h @@ -68,7 +68,7 @@ /* ID and Lock Configuration */ #define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ #define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CFG_FLASH_ID +#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID /* dimensions */ #define CHIP_WIDTH 2 /* chips are in 16 bit mode */ diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S index 41c3a9508e9..b3a089803aa 100644 --- a/board/Marvell/common/misc.S +++ b/board/Marvell/common/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c index 475445b7886..7fbf28a6090 100644 --- a/board/Marvell/common/ns16550.c +++ b/board/Marvell/common/ns16550.c @@ -1,7 +1,7 @@ /* * COM1 NS16550 support * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines + * modified to use CONFIG_SYS_ISA_MEM and new defines * * further modified by Josh Huber <huber@mclx.com> to support * the DUART on the Galileo Eval board. (db64360) @@ -13,8 +13,8 @@ #ifdef ZUMA_NTL /* no 16550 device */ #else -const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), - (NS16550_t) (CFG_DUART_IO + 0x20) +const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0), + (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20) }; volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h index f2ed2abc9eb..b9691ab5afb 100644 --- a/board/Marvell/common/ns16550.h +++ b/board/Marvell/common/ns16550.h @@ -2,7 +2,7 @@ * NS16550 Serial Port * originally from linux source (arch/ppc/boot/ns16550.h) * modified slightly to - * have addresses as offsets from CFG_ISA_BASE + * have addresses as offsets from CONFIG_SYS_ISA_BASE * added a few more definitions * added prototypes for ns16550.c * reduced no of com ports to 2 diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 01efbea77b1..3e7f406ffb1 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -52,17 +52,17 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) int clock_divisor = 230400 / gd->baudrate; #endif mpsc_init (gd->baudrate); /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif return (0); @@ -97,10 +97,10 @@ int serial_init (void) { int clock_divisor = 230400 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 (void) NS16550_init (0, clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 (void) NS16550_init (1, clock_divisor); #endif return (0); @@ -109,29 +109,29 @@ int serial_init (void) void serial_putc (const char c) { if (c == '\n') - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc (void) { - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc (void) { - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void serial_setbrg (void) { int clock_divisor = 230400 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif } diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 2a810a618b0..35b695e8620 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -33,6 +33,7 @@ #include "../include/pci.h" #include "../include/mv_gen_reg.h" #include <net.h> +#include <netdev.h> #include "eth.h" #include "mpsc.h" @@ -54,7 +55,7 @@ /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -63,7 +64,7 @@ */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -126,7 +127,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -135,7 +136,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -153,21 +154,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -183,7 +184,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -199,7 +200,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -250,7 +251,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -296,56 +297,56 @@ int board_early_init_f (void) * on-board sram on the eval board, and updates the correct * registers to boot from the sram. (device0) */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) sram_boot = 1; if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ +#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); #endif -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); #endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); #endif -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -358,7 +359,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd) /* check to see if we booted from the sram. If so, move things * back to the way they should be. (we're running from main * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); } display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -401,7 +402,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -414,34 +415,34 @@ void debug_led (int led, int mode) if (mode == 1) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x08000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x0c000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x10000); break; } } else if (mode == 0) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x14000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x18000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x1c000); break; } @@ -512,7 +513,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -606,7 +607,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -633,9 +634,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -660,8 +661,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -678,9 +679,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -770,8 +771,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -847,9 +848,9 @@ int testdram (void) /* runwalk = 0; */ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -859,7 +860,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -869,7 +870,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -885,7 +886,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -924,8 +925,13 @@ void board_prebootm_init () /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ /* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); icache_disable (); dcache_disable (); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c index 923d95555b2..7ad6ae8c0ed 100644 --- a/board/Marvell/db64360/mpsc.c +++ b/board/Marvell/db64360/mpsc.c @@ -426,7 +426,7 @@ void mpsc_sdma_init (void) (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c index 56372841247..49980951414 100644 --- a/board/Marvell/db64360/pci.c +++ b/board/Marvell/db64360/pci.c @@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); @@ -859,14 +859,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -901,14 +901,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index ecadaf27102..d0817d7e206 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -312,7 +312,7 @@ return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -690,16 +690,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { dimmInfo-> maxClSupported_DDR @@ -714,16 +714,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { printf ("*********************************************************\n"); printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); @@ -1290,37 +1290,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) case 0x0: case 0x80: /* refresh period is 15.625 usec */ sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x1: case 0x81: /* refresh period is 3.9 usec */ sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x2: case 0x82: /* refresh period is 7.8 usec */ sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x3: case 0x83: /* refresh period is 31.3 usec */ sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x4: case 0x84: /* refresh period is 62.5 usec */ sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x5: case 0x85: /* refresh period is 125 usec */ sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; default: /* refresh period undefined */ @@ -1807,7 +1807,7 @@ phys_size_t initdram (int board_type) printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (!checkbank[bank_no]) continue; diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds index 1a95755ab49..ff2d8b7fe44 100644 --- a/board/Marvell/db64360/u-boot.lds +++ b/board/Marvell/db64360/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c index 1ae898d1ee9..14e635592ee 100644 --- a/board/Marvell/db64460/db64460.c +++ b/board/Marvell/db64460/db64460.c @@ -33,6 +33,7 @@ #include "../include/pci.h" #include "../include/mv_gen_reg.h" #include <net.h> +#include <netdev.h> #include "eth.h" #include "mpsc.h" @@ -54,7 +55,7 @@ /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -63,7 +64,7 @@ */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -126,7 +127,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -135,7 +136,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -153,21 +154,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -183,7 +184,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -199,7 +200,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64460 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -250,7 +251,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -296,56 +297,56 @@ int board_early_init_f (void) * on-board sram on the eval board, and updates the correct * registers to boot from the sram. (device0) */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) sram_boot = 1; if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ +#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); #endif -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); #endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); #endif -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -358,7 +359,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd) /* check to see if we booted from the sram. If so, move things * back to the way they should be. (we're running from main * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); } display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -401,7 +402,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -414,34 +415,34 @@ void debug_led (int led, int mode) if (mode == 1) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x08000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x0c000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x10000); break; } } else if (mode == 0) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x14000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x18000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x1c000); break; } @@ -512,7 +513,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -606,7 +607,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -633,9 +634,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -660,8 +661,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -678,9 +679,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -770,8 +771,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -847,9 +848,9 @@ int testdram (void) /* runwalk = 0; */ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -859,7 +860,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -869,7 +870,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -885,7 +886,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -924,8 +925,13 @@ void board_prebootm_init () GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); /* Relocate MV64460 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); icache_disable (); dcache_disable (); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c index 359b8314061..303a63615f7 100644 --- a/board/Marvell/db64460/mpsc.c +++ b/board/Marvell/db64460/mpsc.c @@ -426,7 +426,7 @@ void mpsc_sdma_init (void) (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c index 56372841247..49980951414 100644 --- a/board/Marvell/db64460/pci.c +++ b/board/Marvell/db64460/pci.c @@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); @@ -859,14 +859,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -901,14 +901,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index f36f3484aba..6d6b1264432 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -312,7 +312,7 @@ return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -690,16 +690,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { dimmInfo-> maxClSupported_DDR @@ -714,16 +714,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { printf ("*********************************************************\n"); printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); @@ -1289,37 +1289,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) case 0x0: case 0x80: /* refresh period is 15.625 usec */ sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x1: case 0x81: /* refresh period is 3.9 usec */ sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x2: case 0x82: /* refresh period is 7.8 usec */ sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x3: case 0x83: /* refresh period is 31.3 usec */ sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x4: case 0x84: /* refresh period is 62.5 usec */ sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x5: case 0x85: /* refresh period is 125 usec */ sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; default: /* refresh period undefined */ @@ -1816,7 +1816,7 @@ phys_size_t initdram (int board_type) printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (!checkbank[bank_no]) continue; diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds index 1a95755ab49..ff2d8b7fe44 100644 --- a/board/Marvell/db64460/u-boot.lds +++ b/board/Marvell/db64460/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); |