diff options
| author | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
| commit | 1a247ba7fa5fb09f56892a09a990f03ce564b3e2 (patch) | |
| tree | 9dab0ef013cc6dc7883454808ecf6ba4d7a7a94e /board/MAI/AmigaOneG3SE/start.txt | |
| parent | 2c289e320dcfb3760e99cf1d765cb067194a1202 (diff) | |
| parent | 8155efbd7ae9c65564ca98affe94631d612ae088 (diff) | |
Merge commit 'wd/master'
Diffstat (limited to 'board/MAI/AmigaOneG3SE/start.txt')
| -rw-r--r-- | board/MAI/AmigaOneG3SE/start.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt index e4214622cee..2526ed24ae3 100644 --- a/board/MAI/AmigaOneG3SE/start.txt +++ b/board/MAI/AmigaOneG3SE/start.txt @@ -39,11 +39,11 @@ DIM0_TIM_CTL_0 = 0x737d737d (0xc9) /* DRAM timing control for dimm0 & dimm1; set wait one clock */ - /* cycle for next data access */ + /* cycle for next data access */ DIM2_TIM_CTL_0 = 0x737d737d (0xca) /* DRAM timing control for dimm2 & dimm3; set wait one clock */ - /* cycle for next data access */ + /* cycle for next data access */ DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90) /* set dimm0 bank0 for 128 MB */ |