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authorRick Chen <rick@andestech.com>2019-08-28 18:46:07 +0800
committerAndes <uboot@andestech.com>2019-09-03 09:31:03 +0800
commitedf0acb3b462732cc236f2a8d00abb82abebf38d (patch)
tree32febd7440761cd5a171ce9bcdd109c4dfba1cfb /board/AndesTech
parent4fa4267d82d13eb45cc4202e4439de862e8cad0e (diff)
riscv: ae350: use the v5l2 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'board/AndesTech')
-rw-r--r--board/AndesTech/ax25-ae350/ax25-ae350.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7b754..b43eebb7a61 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <faraday/ftsmc020.h>
#include <fdtdec.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -93,10 +94,18 @@ int smc_init(void)
return 0;
}
+static void v5l2_init(void)
+{
+ struct udevice *dev;
+
+ uclass_get_device(UCLASS_CACHE, 0, &dev);
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
smc_init();
+ v5l2_init();
return 0;
}