diff options
| author | Teresa Remmet <t.remmet@phytec.de> | 2021-10-06 11:56:52 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-10-20 15:09:26 +0200 |
| commit | f38b1da8bbef76505f31bb9cd545d833c8499561 (patch) | |
| tree | 2928cbac1aac7f817d16d35cd086c849acd01a54 /arch | |
| parent | 115732170e4bce54ea0e03ea293b0386f0eafc0a (diff) | |
board: phytec: phycore-imx8mm: Add SPI-NOR flash support
Adds SPI-NOR flash support to erase, read and write in bootloader.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/phycore-imx8mm.dts | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts index a4332619e5f..e57dfd368d6 100644 --- a/arch/arm/dts/phycore-imx8mm.dts +++ b/arch/arm/dts/phycore-imx8mm.dts @@ -54,6 +54,23 @@ }; }; +/* SPI nor flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: norflash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + /* i2c eeprom */ &i2c1 { clock-frequency = <400000>; @@ -140,6 +157,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |