diff options
| author | Stefan Roese <sr@denx.de> | 2018-10-09 08:59:04 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-11-18 16:02:22 +0100 |
| commit | a8b0bf631308fd74a0216b1dc7eb74119303a0b3 (patch) | |
| tree | ef074a2ba981bc231d620b81632434646d249145 /arch | |
| parent | 4751e5595ee1e8ec121178a0ddaa99c3bbfa8e80 (diff) | |
mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init
This fixes an issue which has been noticed on the Gardena board, with
the watchdog enabled, where the watdchdog reset (after a system hang)
did result in reporting of 2.9 GiB and a hang after this. With this
patch applied the memory controller is correctly reset and initialized
again even after a watchdog reset.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/mach-mt7620/lowlevel_init.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S index 1a50f160fe..aa707e0de6 100644 --- a/arch/mips/mach-mt7620/lowlevel_init.S +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -108,6 +108,12 @@ CPLL_READY: sw t3, 0(t0) CPLL_DONE: + /* Reset MC */ + lw t2, 0x34(s0) + ori t2, BIT(10) + sw t2, 0x34(s0) + nop + /* * SDR and DDR initialization: delay 200us */ |