diff options
| author | Vaishnav Achath <vaishnav.a@ti.com> | 2022-10-25 15:14:40 +0530 |
|---|---|---|
| committer | Anand Gadiyar <gadiyar@ti.com> | 2022-11-02 08:51:54 -0500 |
| commit | 713f7328f3bfc45d22b1dfd0f45a90ca35d14446 (patch) | |
| tree | 14e1506d59b13cfe90a48ec14ee91935daaa409b /arch | |
| parent | 1c0d06c606ab2026019e26b8225054216becfdf1 (diff) | |
arm: dts: k3-j784s4-evm: Enable OSPI1 instance for QSPI boot
Enable OSPI1 instance for J784S4 EVM in R5 SPL and A72 SPL,U-Boot.
OSPI1 instance has mt25qu512a QSPI flash connected on J784S4 EVM.
This commit enables the instance and adds the necessary DT entries
and pre-relocation properties to enable the OSP1 controller and
instantiate mt25qu512a flash.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 13 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j784s4-evm.dts | 1 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j784s4-r5-evm.dts | 35 |
3 files changed, 48 insertions, 1 deletions
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi index f9ddf12235..0ce69a1a45 100644 --- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi @@ -169,6 +169,10 @@ u-boot,dm-spl; }; +&mcu_fss0_ospi1_pins_default { + u-boot,dm-spl; +}; + &serdes_ln_ctrl { u-boot,mux-autoprobe; }; @@ -176,6 +180,7 @@ &usb_serdes_mux { u-boot,mux-autoprobe; }; + &ospi0 { u-boot,dm-spl; @@ -191,6 +196,14 @@ }; }; +&ospi1 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + }; +}; + &main_sdhci0 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts index 0f6bd21f45..8e023ec291 100644 --- a/arch/arm/dts/k3-j784s4-evm.dts +++ b/arch/arm/dts/k3-j784s4-evm.dts @@ -906,7 +906,6 @@ }; &ospi1 { - status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts index 6daa55d70f..64cdd71e6e 100644 --- a/arch/arm/dts/k3-j784s4-r5-evm.dts +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -191,6 +191,19 @@ >; }; + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { u-boot,dm-spl; pinctrl-single,pins = < @@ -305,4 +318,26 @@ }; }; +&ospi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + reg = <0x0 0x47050000 0x0 0x100>, + <0x0 0x58000000 0x0 0x8000000>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; #include "k3-j784s4-evm-u-boot.dtsi" |