diff options
| author | Chia-Wei, Wang <chiawei_wang@aspeedtech.com> | 2020-10-15 10:25:13 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-10-22 11:26:14 -0400 |
| commit | 611a28ce271164941aac02feea19f1d87bd1cf32 (patch) | |
| tree | 1a7c3f2a865e5f98a30237d5c0d5434bb57eb96f /arch | |
| parent | fa181d1a95a2851873f586139b7ca3c35c551498 (diff) | |
reset: ast2500: Use SCU for reset control
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/ast2500-u-boot.dtsi | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 51a5244766..ea60e4c8db 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -16,7 +16,6 @@ rst: reset-controller { u-boot,dm-pre-reloc; compatible = "aspeed,ast2500-reset"; - aspeed,wdt = <&wdt1>; #reset-cells = <1>; }; @@ -27,7 +26,7 @@ 0x1e6e0200 0x1d4 >; #reset-cells = <1>; clocks = <&scu ASPEED_CLK_MPLL>; - resets = <&rst AST_RESET_SDRAM>; + resets = <&rst ASPEED_RESET_SDRAM>; }; ahb { @@ -41,7 +40,7 @@ reg = <0x1e740100>; #reset-cells = <1>; clocks = <&scu ASPEED_CLK_SDIO>; - resets = <&rst AST_RESET_SDIO>; + resets = <&rst ASPEED_RESET_SDIO>; }; sdhci1: sdhci@1e740200 { @@ -49,7 +48,7 @@ reg = <0x1e740200>; #reset-cells = <1>; clocks = <&scu ASPEED_CLK_SDIO>; - resets = <&rst AST_RESET_SDIO>; + resets = <&rst ASPEED_RESET_SDIO>; }; }; |