diff options
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2018-01-12 15:35:46 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-01-30 14:29:03 +0100 |
| commit | 3b644a3c2f6925d4e9fb030c11cc8ce3ad472468 (patch) | |
| tree | f5f74cffa399728b5ea945437d68df4d643b7ed2 /arch | |
| parent | f32e79f1595e4565d3b9af44a7f80efd7f017133 (diff) | |
arm64: zynqmp: Provide a config to not map DDR region in MMU table
DDR less systems are possible for configuration like mini qspi
and making DDR region as normal memory may cause speculative
access which results u-boot hang if DDR is absent. So, this
patch fixes the issue by not making DDR memory region
entry into MMU table.
Future solution is to prepare MMU table per memory node in dts instead
of hard code DDR addresses.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/cpu.c | 16 |
2 files changed, 18 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 3f922b4097..46de13054f 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -68,6 +68,12 @@ config PMUFW_INIT_FILE config ZYNQMP_USB bool "Configure ZynqMP USB" +config ZYNQMP_NO_DDR + bool "Disable DDR MMU mapping" + help + This option configures MMU with no DDR to avoid speculative + access to DDR memory where DDR is not present. + config SYS_MALLOC_F_LEN default 0x600 diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 4596d6bff4..bc77dd03c3 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -17,20 +17,24 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region zynqmp_mem_map[] = { +#if !defined(CONFIG_ZYNQMP_NO_DDR) { .virt = 0x0UL, .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { + }, +#endif + { .virt = 0x80000000UL, .phys = 0x80000000UL, .size = 0x70000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, + { .virt = 0xf8000000UL, .phys = 0xf8000000UL, .size = 0x07e00000UL, @@ -52,13 +56,17 @@ static struct mm_region zynqmp_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, +#if !defined(CONFIG_ZYNQMP_NO_DDR) + { .virt = 0x800000000UL, .phys = 0x800000000UL, .size = 0x800000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { + }, +#endif + { .virt = 0x1000000000UL, .phys = 0x1000000000UL, .size = 0xf000000000UL, |