diff options
| author | Hari Nagalla <hnagalla@ti.com> | 2023-01-05 08:00:17 -0600 |
|---|---|---|
| committer | Praneeth Bajjuri <praneeth@ti.com> | 2023-01-05 17:24:05 -0600 |
| commit | 2649852d5bcaae135d73da73bd3297a522abea55 (patch) | |
| tree | 521ea5ad0b979fa5b883f0ec25d3a0d08046dd31 /arch | |
| parent | de65b486d073d0a8c91e622a0a280f3f570866bf (diff) | |
arm: dts: add support for remote procs
AM62A SoC has a C71x DSP and R5F core in main voltage domain and
another R5F core in wakeup domain. The IPC between the R5F, C71x and
A53 processors is through shared memory and mailboxes.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/k3-am62a7-sk.dts | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts index 25c3a6c429..9a85efe093 100644 --- a/arch/arm/dts/k3-am62a7-sk.dts +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -19,6 +19,8 @@ aliases { serial2 = &main_uart0; mmc1 = &sdhci1; + remoteproc0 = &mcu_r5fss0_core0; + remoteproc1 = &c7x_0; }; chosen { @@ -53,6 +55,31 @@ reg = <0x00 0x9c900000 0x00 0x01e00000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0x0e00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0x01efffff>; + no-map; + }; + }; vmain_pd: regulator-0 { @@ -254,6 +281,39 @@ disable-wp; }; +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + mbox_mcu_r5_0: mbox-mcu_r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_gpio0 { status = "okay"; }; |