diff options
| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-07-15 21:47:55 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-07-21 12:45:10 +0200 |
| commit | ef72ba0b87ece8698c7126101f2deeb78c73e357 (patch) | |
| tree | 1123ca8f41309f61a4af16a90622a2571299ce84 /arch | |
| parent | 690c12965f72129838adc1a2465b7a80d4bc2ed3 (diff) | |
sysreset: add support for socfpga sysreset
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.
A side effect is that gen5 and a10 can now select between cold and warm
reset.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager.c | 41 |
3 files changed, 4 insertions, 42 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 51d4acedac4..0fc18138a5a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -895,10 +895,14 @@ config ARCH_SOCFPGA select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 select SPL_SERIAL_SUPPORT + select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT select SUPPORT_SPL select SYS_NS16550 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYSRESET + select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e66720447f8..fc1181cb278 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,7 +8,6 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o -obj-y += reset_manager.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c deleted file mode 100644 index e0a01ed07a5..00000000000 --- a/arch/arm/mach-socfpga/reset_manager.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - */ - - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/reset_manager.h> - -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -#include <asm/arch/mailbox_s10.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; -#endif - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); -#else - writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, - &reset_manager_base->ctrl); -#endif - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} |