Merge git://git.denx.de/u-boot-riscv

1. Improve cache implementation.
2. Fix and improve standalone applications

4 files changed, 31 insertions, 11 deletions

diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index ff4fe640017..84654eb3ed8 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -23,8 +23,7 @@ PLATFORM_LDFLAGS	+= -m $(64bit-emul)
 EFI_LDS			:= elf_riscv64_efi.lds
 endif
 
-CONFIG_STANDALONE_LOAD_ADDR = 0x00000000
-LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/riscv.lds
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
 
 PLATFORM_CPPFLAGS	+= -ffixed-gp -fpic
 PLATFORM_RELFLAGS	+= -fno-common -gdwarf-2 -ffunction-sections \
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 8d6ae170b8c..228fc55f56b 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -6,6 +6,28 @@
 
 #include <common.h>
 
+void flush_dcache_all(void)
+{
+	/*
+	 * Andes' AX25 does not have a coherence agent. U-Boot must use data
+	 * cache flush and invalidate functions to keep data in the system
+	 * coherent.
+	 * The implementation of the fence instruction in the AX25 flushes the
+	 * data cache and is used for this purpose.
+	 */
+	asm volatile ("fence" ::: "memory");
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	flush_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	flush_dcache_all();
+}
+
 void icache_enable(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index ae5c60716ff..5437a122a10 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -11,13 +11,12 @@ void invalidate_icache_all(void)
 	asm volatile ("fence.i" ::: "memory");
 }
 
-void flush_dcache_all(void)
+__weak void flush_dcache_all(void)
 {
-	asm volatile ("fence" :::"memory");
 }
-void flush_dcache_range(unsigned long start, unsigned long end)
+
+__weak void flush_dcache_range(unsigned long start, unsigned long end)
 {
-	flush_dcache_all();
 }
 
 void invalidate_icache_range(unsigned long start, unsigned long end)
@@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end)
 	invalidate_icache_all();
 }
 
-void invalidate_dcache_range(unsigned long start, unsigned long end)
+__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
-	flush_dcache_all();
 }
 
 void cache_flush(void)
@@ -42,8 +40,8 @@ void cache_flush(void)
 
 void flush_cache(unsigned long addr, unsigned long size)
 {
-	invalidate_icache_all();
-	flush_dcache_all();
+	invalidate_icache_range(addr, addr + size);
+	flush_dcache_range(addr, addr + size);
 }
 
 __weak void icache_enable(void)
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e185933b01e..74c1e561c71 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -37,7 +37,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 		printf("exception code: %ld , %s , epc %lx , ra %lx\n",
 		       code, exception_code[code], epc, regs->ra);
 	} else {
-		printf("Reserved\n");
+		printf("reserved exception code: %ld , epc %lx , ra %lx\n",
+		       code, epc, regs->ra);
 	}
 
 	hang();