diff options
| author | Ye Li <ye.li@nxp.com> | 2017-07-27 20:53:06 -0500 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2017-11-03 02:37:05 +0800 |
| commit | 12958cc075d35d62492a64cf33e5839f3ec0cc1c (patch) | |
| tree | a2e4d91935b739e1d45ad463daf07f69dd8491bf /arch | |
| parent | f23c267c733e62758b56615f569637fd3479005d (diff) | |
MLK-16094-3 imx8qxp_arm2/mek: Update codes to use pinctrl driver
This patch enables the pinctrl driver for i.MX8QXP ARM2 and MEK boards.
For DM enabled driver, the iomux pins can be set by pinctrl driver. So
the board codes don't need to set iomux explicitly for these DM enabled modules.
Also update the DTS file for i2c pins settings.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts | 16 | ||||
| -rw-r--r-- | arch/arm/dts/fsl-imx8qxp-mek.dts | 16 |
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts index 8637bf1ecc0..2683513db38 100644 --- a/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-arm2.dts @@ -179,6 +179,20 @@ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c >; }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; }; }; @@ -285,6 +299,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; clock-frequency = <100000>; status = "okay"; @@ -298,6 +313,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; clock-frequency = <100000>; status = "okay"; diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts index cac6c665fcb..8b051ab4efa 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek.dts +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -212,6 +212,20 @@ SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c >; }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; }; }; @@ -345,6 +359,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; clock-frequency = <100000>; status = "okay"; }; @@ -353,6 +368,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; clock-frequency = <100000>; status = "okay"; }; |