board_f: Rename initdram() to dram_init()

This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini <trini@konsulko.com>

12 files changed, 36 insertions, 19 deletions

diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index d1f10abb68..cb80893337 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -28,3 +28,9 @@ int arch_early_init_r(void)
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
+
+/* This is a dummy function on arc */
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c
index 1c73addcb3..2706812b91 100644
--- a/arch/mips/mach-ath79/dram.c
+++ b/arch/mips/mach-ath79/dram.c
@@ -11,7 +11,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int initdram(void)
+int dram_init(void)
 {
 	ddr_tap_tuning();
 	gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index c96e046848..c3194f0a39 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -110,7 +110,7 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-int initdram(void)
+int dram_init(void)
 {
 	ddr2_pmd_ungate();
 	ddr2_phy_init();
diff --git a/arch/mips/mach-pic32/include/mach/ddr.h b/arch/mips/mach-pic32/include/mach/ddr.h
index 00abfa3ca9..e7da807d66 100644
--- a/arch/mips/mach-pic32/include/mach/ddr.h
+++ b/arch/mips/mach-pic32/include/mach/ddr.h
@@ -8,7 +8,7 @@
 #ifndef __MICROCHIP_PIC32_DDR_H
 #define __MICROCHIP_PIC32_DDR_H
 
-/* called by initdram() function */
+/* called by dram_init() function */
 void ddr2_phy_init(void);
 void ddr2_ctrl_init(void);
 phys_size_t ddr2_calculate_size(void);
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index c1caa65174..6c4ec2cea4 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -150,3 +150,9 @@ U_BOOT_DRIVER(altera_nios2) = {
 	.ops		= &altera_nios2_ops,
 	.flags		= DM_FLAG_PRE_RELOC,
 };
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
index 23d2010343..2d7f6c4a93 100644
--- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c
+++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
@@ -32,7 +32,7 @@ void board_init_f(ulong bootflag)
 	/*
 	 * On MPC5200, the initial RAM (and gd) is located in the internal
 	 * SRAM. So we can actually call the preloader console init code
-	 * before calling initdram(). This makes serial output (printf)
+	 * before calling dram_init(). This makes serial output (printf)
 	 * available very early, even before SDRAM init, which has been
 	 * an U-Boot priciple from day 1.
 	 */
@@ -62,7 +62,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram();
+	dram_init();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 64e0aa7518..e3ef4ae816 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -401,7 +401,7 @@ void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
-int initdram(void)
+int dram_init(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
 	defined(CONFIG_ARCH_QEMU_E500)
@@ -413,7 +413,7 @@ int initdram(void)
 	return 0;
 }
 #else /* CONFIG_SYS_RAMBOOT */
-int initdram(void)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 87fd5e65e0..ffc62a5849 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -403,20 +403,20 @@ static unsigned char spd_read(uchar chip, uint addr)
 }
 
 /*-----------------------------------------------------------------------------+
- * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * dram_init.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
  * Note: This routine runs from flash with a stack set up in the chip's
  * sram space.  It is important that the routine does not require .sbss, .bss or
  * .data sections.  It also cannot call routines that require these sections.
  *-----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
- * Function:	 initdram
+ * Function:	 dram_init
  * Description:  Configures SDRAM memory banks for DDR operation.
  *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  *		 via the IIC bus and then configures the DDR SDRAM memory
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
 {
 	unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -2855,13 +2855,13 @@ static void test(void)
 #else /* CONFIG_SPD_EEPROM */
 
 /*-----------------------------------------------------------------------------
- * Function:	initdram
+ * Function:	dram_init
  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
  * 		The configuration is performed using static, compile-
  *		time parameters.
  * 		Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
 {
 	unsigned long val;
 
diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
index 14d0fd9154..c477853fb8 100644
--- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
@@ -987,20 +987,20 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
 }
 
 /*-----------------------------------------------------------------------------+
- * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
+ * dram_init.  Initializes the 440EPx/GPx DDR SDRAM controller.
  * Note: This routine runs from flash with a stack set up in the chip's
  * sram space.  It is important that the routine does not require .sbss, .bss or
  * .data sections.  It also cannot call routines that require these sections.
  *-----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
- * Function:	 initdram
+ * Function:	 dram_init
  * Description:  Configures SDRAM memory banks for DDR operation.
  *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  *		 via the IIC bus and then configures the DDR SDRAM memory
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-int initdram(void)
+int dram_init(void)
 {
 	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_ranks[MAXDIMMS];
@@ -1014,7 +1014,7 @@ int initdram(void)
 	unsigned long cas_latency = 0;	/* to quiet initialization warning */
 	unsigned long dram_size;
 
-	debug("\nEntering initdram()\n");
+	debug("\nEntering dram_init()\n");
 
 	/*------------------------------------------------------------------
 	 * Stop the DDR-SDRAM controller.
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index a49bd69aba..c416bcebf6 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -150,7 +150,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 /*
  * Autodetect onboard SDRAM on 405 platforms
  */
-int initdram(void)
+int dram_init(void)
 {
 	ulong speed;
 	ulong sdtr1;
@@ -353,7 +353,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
  *	 so this should be extended for other future boards
  *	 using this routine!
  */
-int initdram(void)
+int dram_init(void)
 {
 	int i;
 	int tr1_bank1;
diff --git a/arch/powerpc/cpu/ppc4xx/spl_boot.c b/arch/powerpc/cpu/ppc4xx/spl_boot.c
index f3aa46c4f1..b30f169e89 100644
--- a/arch/powerpc/cpu/ppc4xx/spl_boot.c
+++ b/arch/powerpc/cpu/ppc4xx/spl_boot.c
@@ -26,7 +26,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram();
+	dram_init();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);
diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c
index 6787a6182c..7044480597 100644
--- a/arch/xtensa/cpu/cpu.c
+++ b/arch/xtensa/cpu/cpu.c
@@ -47,3 +47,8 @@ int arch_cpu_init(void)
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }
+
+int dram_init(void)
+{
+	return 0;
+}