diff options
| author | Vignesh Raghavendra <vigneshr@ti.com> | 2020-08-07 00:27:01 +0530 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-08-11 20:34:46 +0530 |
| commit | db6451ec0e8483f76f3364293d48e86249c52322 (patch) | |
| tree | 17c7cb1755b6ca143a254a77725938a45e554e11 /arch | |
| parent | 4bb4b069839bf80511e76a5b4fcc6b13ff927efb (diff) | |
arm: dts: k3-j7200-common-proc-board: Enable CPSW2G port
Enable CPSW2G port to support networking in U-Boot
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 15 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j7200-common-proc-board.dts | 43 |
2 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 4dca59cefa..4972a7559f 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -9,6 +9,9 @@ tick-timer = &timer1; }; + aliases { + ethernet0 = &cpsw_port1; + }; }; &chipid { @@ -103,6 +106,18 @@ u-boot,dm-spl; }; +&mcu_cpsw { + reg = <0x0 0x46000000 0x0 0x200000>, + <0x0 0x40f00200 0x0 0x8>; + reg-names = "cpsw_nuss", "mac_efuse"; + + cpsw-phy-sel@40f04040 { + compatible = "ti,am654-cpsw-phy-sel"; + reg= <0x0 0x40f04040 0x0 0x4>; + reg-names = "gmii-sel"; + }; +}; + &main_usbss0_pins_default { u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 15ac3cb6b3..3f1d03c960 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/net/ti-dp83867.h> #include "k3-j7200-som-p0.dtsi" / { @@ -27,6 +28,30 @@ J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ >; }; + + mcu_cpsw_pins_default: mcu_cpsw_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + >; + }; + + mcu_mdio_pins_default: mcu_mdio1_pins_default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + >; + }; }; &main_pmx0 { @@ -150,3 +175,21 @@ pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; |