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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-07-28 12:26:21 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-07-28 12:26:21 +0200
commitb1cdd8baa14f518288ceddb391d6587c1ecb3174 (patch)
treec3d00b3193b2ee86b9679baf1933b10a7d07a13d /arch
parent48b3ed217f58487c583d59575d7dfe2aafbb738d (diff)
parent434f2cfcad9f70231ad5a096325ba72ef0d2a2cc (diff)
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/keystone/Makefile5
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2e.c101
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2hk.c113
-rw-r--r--arch/arm/cpu/armv7/keystone/clock.c154
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_clock.c31
-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c25
-rw-r--r--arch/arm/cpu/armv7/keystone/init.c16
-rw-r--r--arch/arm/cpu/armv7/keystone/keystone.c87
-rw-r--r--arch/arm/cpu/armv7/keystone/msmc.c6
-rw-r--r--arch/arm/cpu/armv7/keystone/psc.c42
-rw-r--r--arch/arm/cpu/armv7/keystone/spl.c8
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c3
-rw-r--r--arch/arm/cpu/armv7/omap-common/mem-common.c15
-rw-r--r--arch/arm/cpu/armv7/omap3/mem.c139
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h4
-rw-r--r--arch/arm/include/asm/arch-am33xx/mem.h7
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2e.h68
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2hk.h23
-rw-r--r--arch/arm/include/asm/arch-keystone/clock.h32
-rw-r--r--arch/arm/include/asm/arch-keystone/clock_defs.h2
-rw-r--r--arch/arm/include/asm/arch-keystone/ddr3.h56
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2e.h44
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h182
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h117
-rw-r--r--arch/arm/include/asm/arch-keystone/mon.h15
-rw-r--r--arch/arm/include/asm/arch-keystone/msmc.h17
-rw-r--r--arch/arm/include/asm/arch-omap3/cpu.h1
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h13
-rw-r--r--arch/arm/include/asm/omap_common.h8
29 files changed, 813 insertions, 521 deletions
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index c4af2521102..f8519c04035 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -8,9 +8,12 @@
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
+obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
-obj-y += keystone_nav.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += ddr3.o
+obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
new file mode 100644
index 00000000000..42092e1060d
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case DDR3_PLL:
+ ret = external_clk[ddr3_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
new file mode 100644
index 00000000000..96a9f728861
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
@@ -0,0 +1,113 @@
+/*
+ * Keystone2: get clk rate for K2HK
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+ [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+ [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll: pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+ unsigned long mult = 1, prediv = 1, output_div = 2;
+ unsigned long ret;
+ u32 tmp, reg;
+
+ if (pll == CORE_PLL) {
+ ret = external_clk[sys_clk];
+ if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+ /* PLL mode */
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+ (pllctl_reg_read(pll, mult) &
+ PLLM_MULT_LO_MASK)) + 1;
+ output_div = ((pllctl_reg_read(pll, secctl) >>
+ PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+ ret = ret / prediv / output_div * mult;
+ }
+ } else {
+ switch (pll) {
+ case PASS_PLL:
+ ret = external_clk[pa_clk];
+ reg = KS2_PASSPLLCTL0;
+ break;
+ case TETRIS_PLL:
+ ret = external_clk[tetris_clk];
+ reg = KS2_ARMPLLCTL0;
+ break;
+ case DDR3A_PLL:
+ ret = external_clk[ddr3a_clk];
+ reg = KS2_DDR3APLLCTL0;
+ break;
+ case DDR3B_PLL:
+ ret = external_clk[ddr3b_clk];
+ reg = KS2_DDR3BPLLCTL0;
+ break;
+ default:
+ return 0;
+ }
+
+ tmp = __raw_readl(reg);
+
+ if (!(tmp & PLLCTL_BYPASS)) {
+ /* Bypass disabled */
+ prediv = (tmp & PLL_DIV_MASK) + 1;
+ mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+ output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+ PLL_CLKOD_MASK) + 1;
+ ret = ((ret / prediv) * mult) / output_div;
+ }
+ }
+
+ return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+ switch (clk) {
+ case core_pll_clk: return pll_freq_get(CORE_PLL);
+ case pass_pll_clk: return pll_freq_get(PASS_PLL);
+ case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
+ case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
+ case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
+ case sys_clk0_1_clk:
+ case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
+ case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
+ case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
+ case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
+ case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
+ case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
+ case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
+ case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
+ case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
+ case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
+ case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
+ case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
+ case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
+ case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
+ case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d8f6a..03c1d9f660f 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -8,9 +8,6 @@
*/
#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
@@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data)
}
}
-struct pll_regs {
- u32 reg0, reg1;
-};
-
-static const struct pll_regs pll_regs[] = {
- [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
- [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
- [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
- [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
- [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
-};
-
-/* Fout = Fref * NF(mult) / NR(prediv) / OD */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(K2HK_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = K2HK_PASSPLLCTL0;
- break;
- case TETRIS_PLL:
- ret = external_clk[tetris_clk];
- reg = K2HK_ARMPLLCTL0;
- break;
- case DDR3A_PLL:
- ret = external_clk[ddr3a_clk];
- reg = K2HK_DDR3APLLCTL0;
- break;
- case DDR3B_PLL:
- ret = external_clk[ddr3b_clk];
- reg = K2HK_DDR3BPLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
-
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
- case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
- case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
- return 0;
-}
-
void init_pll(const struct pll_init_data *data)
{
u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
@@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data)
tmp = pllctl_reg_read(data->pll, secctl);
if (tmp & (PLLCTL_BYPASS)) {
- setbits_le32(pll_regs[data->pll].reg1,
+ setbits_le32(keystone_pll_regs[data->pll].reg1,
BIT(MAIN_ENSAT_OFFSET));
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
@@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data)
pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
- clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
- (pllm << 6));
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ PLLM_MULT_HI_SMASK, (pllm << 6));
/* Set the BWADJ (12 bit field) */
tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
- clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ PLL_BWADJ_LO_SMASK,
(tmp_ctl << PLL_BWADJ_LO_SHIFT));
- clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+ PLL_BWADJ_HI_MASK,
(tmp_ctl >> 8));
/*
* Set the pll divider (6 bit field) *
* PLLD[5:0] is located in MAINPLLCTL0
*/
- clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+ clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+ PLL_DIV_MASK, plld);
/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
@@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data)
tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+#ifndef CONFIG_SOC_K2E
} else if (data->pll == TETRIS_PLL) {
bwadj = pllm >> 1;
/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
* only applicable for Kepler
*/
- clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(pll_regs[data->pll].reg1 ,
+ setbits_le32(keystone_pll_regs[data->pll].reg1 ,
PLL_PLLRST | PLLCTL_ENSAT);
/*
@@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data)
(pllm << 6) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, pll_regs[data->pll].reg0);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
- tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, pll_regs[data->pll].reg1);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/*
* 5 Wait for at least 5 us based on the reference
* clock (PLL reset time)
@@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data)
sdelay(21000); /* Wait for a minimum of 7 us*/
/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+ clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
/*
* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
* (PLL lock time)
*/
sdelay(105000);
/* 8 disable bypass */
- clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
* only applicable for Kepler
*/
- setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
+#endif
} else {
- setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+ setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
/*
* process keeps state of Bypass bit while programming
* all other DDR PLL settings
*/
- tmp = __raw_readl(pll_regs[data->pll].reg0);
+ tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
/*
@@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data)
(pllm << PLL_MULT_SHIFT) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT);
- __raw_writel(tmp, pll_regs[data->pll].reg0);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
- tmp = __raw_readl(pll_regs[data->pll].reg1);
+ tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
@@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data)
if (data->pll == PASS_PLL)
tmp |= PLLCTL_PAPLL;
- __raw_writel(tmp, pll_regs[data->pll].reg1);
+ __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
tmp = PLL_PLLRST;
/* Set RESET bit = 1 */
- setbits_le32(pll_regs[data->pll].reg1, tmp);
+ setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
/* Wait for a minimum of 7 us*/
sdelay(21000);
/* Clear RESET bit */
- clrbits_le32(pll_regs[data->pll].reg1, tmp);
+ clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
sdelay(105000);
/* clear BYPASS (Enable PLL Mode) */
- clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+ clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
sdelay(21000); /* Wait for a minimum of 7 us*/
}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
index afd30f38534..d97c95be11d 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -14,10 +14,10 @@
#include <asm/arch/psc_defs.h>
struct pll_init_data cmd_pll_data = {
- .pll = MAIN_PLL,
- .pll_m = 16,
- .pll_d = 1,
- .pll_od = 2,
+ .pll = MAIN_PLL,
+ .pll_m = 16,
+ .pll_d = 1,
+ .pll_od = 2,
};
int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (strncmp(argv[1], "pa", 2) == 0)
cmd_pll_data.pll = PASS_PLL;
+#ifndef CONFIG_SOC_K2E
else if (strncmp(argv[1], "arm", 3) == 0)
cmd_pll_data.pll = TETRIS_PLL;
+#endif
+#ifdef CONFIG_SOC_K2HK
else if (strncmp(argv[1], "ddr3a", 5) == 0)
cmd_pll_data.pll = DDR3A_PLL;
else if (strncmp(argv[1], "ddr3b", 5) == 0)
cmd_pll_data.pll = DDR3B_PLL;
+#else
+ else if (strncmp(argv[1], "ddr3", 4) == 0)
+ cmd_pll_data.pll = DDR3_PLL;
+#endif
else
goto pll_cmd_usage;
@@ -51,11 +58,20 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
+#ifdef CONFIG_SOC_K2HK
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
);
+#endif
+#ifdef CONFIG_SOC_K2E
+U_BOOT_CMD(
+ pllset, 5, 0, do_pll_cmd,
+ "set pll multiplier and pre divider",
+ "<pa|ddr3> <mult> <div> <OD>\n"
+);
+#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -79,7 +95,12 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
- "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+#ifdef CONFIG_SOC_K2HK
+ "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
+#endif
+#ifdef CONFIG_SOC_K2E
+ "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
+#endif
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index 4875db76a35..2391e794e89 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -7,10 +7,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/arch/hardware.h>
#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/ddr3.h>
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
}
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
@@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
+
+void ddr3_reset_ddrphy(void)
+{
+ u32 tmp;
+
+ /* Assert DDR3A PHY reset */
+ tmp = readl(KS2_DDR3APLLCTL1);
+ tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
+ writel(tmp, KS2_DDR3APLLCTL1);
+
+ /* wait 10us to catch the reset */
+ udelay(10);
+
+ /* Release DDR3A PHY reset */
+ tmp = readl(KS2_DDR3APLLCTL1);
+ tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
+ __raw_writel(tmp, KS2_DDR3APLLCTL1);
+}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae9..a8f8aee8ab4 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,13 +10,14 @@
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
+#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
void chip_configuration_unlock(void)
{
- __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
- __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+ __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+ __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
int arch_cpu_init(void)
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
chip_configuration_unlock();
icache_enable();
-#ifdef CONFIG_SOC_K2HK
- share_all_segments(8);
- share_all_segments(9);
- share_all_segments(10); /* QM PDSP */
- share_all_segments(11); /* PCIE */
+ msmc_share_all_segments(8); /* TETRIS */
+ msmc_share_all_segments(9); /* NETCP */
+ msmc_share_all_segments(10); /* QM PDSP */
+ msmc_share_all_segments(11); /* PCIE 0 */
+#ifdef CONFIG_SOC_K2E
+ msmc_share_all_segments(13); /* PCIE 1 */
#endif
/*
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
new file mode 100644
index 00000000000..11a9357db41
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -0,0 +1,87 @@
+/*
+ * Keystone EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/hardware.h>
+
+/**
+ * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
+ * @ptr - array of data
+ * @length - lenght of data array
+ */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+ u32 i;
+
+ if (!(readl(KS2_DEVSTAT) & 0x1))
+ for (i = 0; i < length; i++, ptr++)
+ *ptr = cpu_to_be32(*ptr);
+
+ return 0;
+}
+
+static int turn_off_myself(void)
+{
+ printf("Turning off ourselves\r\n");
+ mon_power_off(0);
+
+ psc_disable_module(KS2_LPSC_TETRIS);
+ psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+ asm volatile ("isb\n"
+ "dsb\n"
+ "wfi\n");
+
+ printf("What! Should not see that\n");
+ return 0;
+}
+
+static void turn_off_all_dsps(int num_dsps)
+{
+ int i;
+
+ for (i = 0; i < num_dsps; i++) {
+ if (psc_disable_module(i + KS2_LPSC_GEM_0))
+ printf("Cannot disable module for #%d DSP", i);
+
+ if (psc_disable_domain(i + 8))
+ printf("Cannot disable domain for #%d DSP", i);
+ }
+}
+
+int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return turn_off_myself();
+}
+
+U_BOOT_CMD(
+ killme, 1, 0, do_killme_cmd,
+ "turn off main ARM core",
+ "turn off main ARM core. Should not live after that :(\n"
+);
+
+int misc_init_r(void)
+{
+ char *env;
+ long ks2_debug = 0;
+
+ env = getenv("ks2_debug");
+
+ if (env)
+ ks2_debug = simple_strtol(env, NULL, 0);
+
+ if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
+ turn_off_all_dsps(KS2_NUM_DSPS);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index f3f1621d205..7d8e5978dfa 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -8,7 +8,7 @@
*/
#include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/msmc.h>
struct mpax {
u32 mpaxl;
@@ -56,9 +56,9 @@ struct msms_regs {
};
-void share_all_segments(int priv_id)
+void msmc_share_all_segments(int priv_id)
{
- struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
for (j = 0; j < 8; j++) {
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
index c844dc84d50..fa5422f2e8b 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/cpu/armv7/keystone/psc.c
@@ -16,10 +16,6 @@
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
-#ifdef CONFIG_SOC_K2HK
-#define DEVICE_PSC_BASE K2HK_PSC_BASE
-#endif
-
int psc_delay(void)
{
udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
retry = 0;
do {
- ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+ ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
/* Get the power domain associated with the module number */
- domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
- v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
- pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+ pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
- ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
/* Set the reset isolation bit */
- mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
- v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+ v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
@@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
u32 pdctl;
u32 ptcmd;
- pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+ pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
- ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
- DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+ DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}
diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c
index e07b64db9ee..d4b0e9b163e 100644
--- a/arch/arm/cpu/armv7/keystone/spl.c
+++ b/arch/arm/cpu/armv7/keystone/spl.c
@@ -18,10 +18,18 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_K2HK_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+#endif
void spl_init_keystone_plls(void)
{
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 5f50a198015..1b4477f4690 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -123,7 +123,8 @@ void s_init(void)
hw_data_init();
#ifdef CONFIG_SPL_BUILD
- if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+ if (warm_reset() &&
+ (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
force_emif_self_refresh();
#endif
watchdog_init();
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index 5bc7e1f19b3..fc4290c3c4e 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -87,9 +87,13 @@ void gpmc_init(void)
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
- u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
-#elif defined(CONFIG_NAND)
+ u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
+ /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
+ /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
+ /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
+ /* min 16MB */ GPMC_SIZE_16M)));
+#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
@@ -99,8 +103,9 @@ void gpmc_init(void)
M_NAND_GPMC_CONFIG6,
0
};
- u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
+ u32 size = GPMC_SIZE_16M;
+
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
@@ -110,8 +115,8 @@ void gpmc_init(void)
ONENAND_GPMC_CONFIG6,
0
};
- u32 base = PISMO1_ONEN_BASE;
- u32 size = PISMO1_ONEN_SIZE;
+ u32 size = GPMC_SIZE_128M;
+ u32 base = CONFIG_SYS_ONENAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
deleted file mode 100644
index 1832affa5bb..00000000000
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Initial Code from:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-struct gpmc *gpmc_cfg;
-
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
- M_NAND_GPMC_CONFIG1,
- M_NAND_GPMC_CONFIG2,
- M_NAND_GPMC_CONFIG3,
- M_NAND_GPMC_CONFIG4,
- M_NAND_GPMC_CONFIG5,
- M_NAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_CMD_ONENAND)
-static const u32 gpmc_onenand[GPMC_MAX_REG] = {
- ONENAND_GPMC_CONFIG1,
- ONENAND_GPMC_CONFIG2,
- ONENAND_GPMC_CONFIG3,
- ONENAND_GPMC_CONFIG4,
- ONENAND_GPMC_CONFIG5,
- ONENAND_GPMC_CONFIG6, 0
-};
-#endif /* CONFIG_CMD_ONENAND */
-
-/********************************************************
- * mem_ok() - test used to see if timings are correct
- * for a part. Helps in guessing which part
- * we are currently using.
- *******************************************************/
-u32 mem_ok(u32 cs)
-{
- u32 val1, val2, addr;
- u32 pattern = 0x12345678;
-
- addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
-
- writel(0x0, addr + 0x400); /* clear pos A */
- writel(pattern, addr); /* pattern to pos B */
- writel(0x0, addr + 4); /* remove pattern off the bus */
- val1 = readl(addr + 0x400); /* get pos A value */
- val2 = readl(addr); /* get val2 */
- writel(0x0, addr + 0x400); /* clear pos A */
-
- if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
- return 0;
- else
- return 1;
-}
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
- u32 size)
-{
- writel(0, &cs->config7);
- sdelay(1000);
- /* Delay for settling */
- writel(gpmc_config[0], &cs->config1);
- writel(gpmc_config[1], &cs->config2);
- writel(gpmc_config[2], &cs->config3);
- writel(gpmc_config[3], &cs->config4);
- writel(gpmc_config[4], &cs->config5);
- writel(gpmc_config[5], &cs->config6);
-
- /*
- * Enable the config. size is the CS size and goes in
- * bits 11:8. We set bit 6 to enable this CS and the base
- * address goes into bits 5:0.
- */
- writel((size << 8) | (GPMC_CS_ENABLE << 6) |
- ((base >> 24) & GPMC_BASEADDR_MASK),
- &cs->config7);
- sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
- /* putting a blanket check on GPMC based on ZeBu for now */
- gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
- const u32 *gpmc_config = NULL;
- u32 base = 0;
- u32 size = 0;
-#endif
- u32 config = 0;
-
- /* global settings */
- writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
- writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
- config = readl(&gpmc_cfg->config);
- config &= (~0xf00);
- writel(config, &gpmc_cfg->config);
-
- /*
- * Disable the GPMC0 config set by ROM code
- * It conflicts with our MPDB (both at 0x08000000)
- */
- writel(0, &gpmc_cfg->cs[0].config7);
- sdelay(1000);
-
-#if defined(CONFIG_CMD_NAND) /* CS 0 */
- gpmc_config = gpmc_m_nand;
-
- base = PISMO1_NAND_BASE;
- size = PISMO1_NAND_SIZE;
- enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
- gpmc_config = gpmc_onenand;
- base = PISMO1_ONEN_BASE;
- size = PISMO1_ONEN_SIZE;
- enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
-}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 4d899528f5b..97bbfe2e65e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -33,11 +33,7 @@
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_RATIO 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
-#define MT47H128M16RT25E_WR_DQS 0x00
-#define MT47H128M16RT25E_PHY_WRLVL 0x00
-#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index e7e8c58b000..b2412b56e15 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -59,13 +59,6 @@
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
-#define PISMO1_NOR 1
-#define PISMO1_NAND 2
-#define PISMO2_CS0 3
-#define PISMO2_CS1 4
-#define PISMO1_ONENAND 5
#define DBG_MPDB 6
-#define PISMO2_NAND_CS0 7
-#define PISMO2_NAND_CS1 8
#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
new file mode 100644
index 00000000000..41478110e5a
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -0,0 +1,68 @@
+/*
+ * K2E: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2E_H
+#define __ASM_ARCH_CLOCK_K2E_H
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ ddr3_clk,
+ mcm_clk,
+ pcie_clk,
+ sgmii_clk,
+ xgmii_clk,
+ usb_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+ core_pll_clk,
+ pass_pll_clk,
+ ddr3_pll_clk,
+ sys_clk0_clk,
+ sys_clk0_1_clk,
+ sys_clk0_2_clk,
+ sys_clk0_3_clk,
+ sys_clk0_4_clk,
+ sys_clk0_6_clk,
+ sys_clk0_8_clk,
+ sys_clk0_12_clk,
+ sys_clk0_24_clk,
+ sys_clk1_clk,
+ sys_clk1_3_clk,
+ sys_clk1_4_clk,
+ sys_clk1_6_clk,
+ sys_clk1_12_clk,
+ sys_clk2_clk,
+ sys_clk3_clk
+};
+
+#define KS2_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ DDR3_PLL,
+};
+
+#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
+#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
+#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
+#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
+#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index 6a69a8d2bed..784a0be5675 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -10,10 +10,6 @@
#ifndef __ASM_ARCH_CLOCK_K2HK_H
#define __ASM_ARCH_CLOCK_K2HK_H
-#include <asm/arch/hardware.h>
-
-#ifndef __ASSEMBLY__
-
enum ext_clk_e {
sys_clk,
alt_core_clk,
@@ -56,7 +52,7 @@ enum clk_e {
sys_clk3_clk
};
-#define K2HK_CLK1_6 sys_clk0_6_clk
+#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
@@ -66,15 +62,6 @@ enum pll_type_e {
DDR3A_PLL,
DDR3B_PLL,
};
-#define MAIN_PLL CORE_PLL
-
-/* PLL configuration data */
-struct pll_init_data {
- int pll;
- int pll_m; /* PLL Multiplier */
- int pll_d; /* PLL divider */
- int pll_od; /* PLL output divider */
-};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
@@ -98,12 +85,4 @@ struct pll_init_data {
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
-void init_plls(int num_pll, struct pll_init_data *config);
-void init_pll(const struct pll_init_data *data);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-#endif
-
#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
index 324501b75ae..1513c76b6a0 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -10,8 +10,40 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#ifndef __ASSEMBLY__
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/clock-k2hk.h>
#endif
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/clock-k2e.h>
+#endif
+
+#define MAIN_PLL CORE_PLL
+
+#include <asm/types.h>
+
+struct keystone_pll_regs {
+ u32 reg0;
+ u32 reg1;
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+ int pll;
+ int pll_m; /* PLL Multiplier */
+ int pll_d; /* PLL divider */
+ int pll_od; /* PLL output divider */
+};
+
+extern const struct keystone_pll_regs keystone_pll_regs[];
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h
index b251aff3832..e545341ca7c 100644
--- a/arch/arm/include/asm/arch-keystone/clock_defs.h
+++ b/arch/arm/include/asm/arch-keystone/clock_defs.h
@@ -50,7 +50,7 @@ struct pllctl_regs {
};
static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x100)
+ (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
new file mode 100644
index 00000000000..4d229a25fa1
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -0,0 +1,56 @@
+/*
+ * DDR3
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDR3_H_
+#define _DDR3_H_
+
+#include <asm/arch/hardware.h>
+
+struct ddr3_phy_config {
+ unsigned int pllcr;
+ unsigned int pgcr1_mask;
+ unsigned int pgcr1_val;
+ unsigned int ptr0;
+ unsigned int ptr1;
+ unsigned int ptr2;
+ unsigned int ptr3;
+ unsigned int ptr4;
+ unsigned int dcr_mask;
+ unsigned int dcr_val;
+ unsigned int dtpr0;
+ unsigned int dtpr1;
+ unsigned int dtpr2;
+ unsigned int mr0;
+ unsigned int mr1;
+ unsigned int mr2;
+ unsigned int dtcr;
+ unsigned int pgcr2;
+ unsigned int zq0cr1;
+ unsigned int zq1cr1;
+ unsigned int zq2cr1;
+ unsigned int pir_v1;
+ unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+ unsigned int sdcfg;
+ unsigned int sdtim1;
+ unsigned int sdtim2;
+ unsigned int sdtim3;
+ unsigned int sdtim4;
+ unsigned int zqcfg;
+ unsigned int sdrfc;
+};
+
+void ddr3_init(void);
+void ddr3_reset_ddrphy(void);
+void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
new file mode 100644
index 00000000000..62172a4b84d
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
@@ -0,0 +1,44 @@
+/*
+ * K2E: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2E_H
+#define __ASM_ARCH_HARDWARE_K2E_H
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x24000000
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_MOD_RST 0
+#define KS2_LPSC_USB_1 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE 10
+#define KS2_LPSC_VUSR0 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_EMIF4F_DDR3 23
+#define KS2_LPSC_PCIE_1 27
+#define KS2_LPSC_XGE 50
+
+/* Chip Interrupt Controller */
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
+
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 1
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 50ce649d4c0..eb132f73e60 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -6,136 +6,82 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define K2HK_PLL_CNTRL_BASE 0x02310000
-#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
-#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_KEY 0x5a69
-#define KS2_RSTCTRL_MASK 0xffff0000
-#define KS2_RSTCTRL_SWRST 0xfffe0000
-
-#define K2HK_PSC_BASE 0x02350000
-#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
-#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-
-#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
-#define ARM_PLL_EN BIT(13)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-#define K2HK_SPI0_BASE 0x21000400
-#define K2HK_SPI1_BASE 0x21000600
-#define K2HK_SPI2_BASE 0x21000800
-#define K2HK_SPI_BASE K2HK_SPI0_BASE
-
-/* Chip configuration unlock codes and registers */
-#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KEYSTONE_KICK0_MAGIC 0x83e70b13
-#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
+#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
-#define KS2_PASS_BASE 0x02000000
+#define KS2_PASS_BASE 0x02000000
/* PLL control registers */
-#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
-#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
/* Power and Sleep Controller (PSC) Domains */
-#define K2HK_LPSC_MOD 0
-#define K2HK_LPSC_DUMMY1 1
-#define K2HK_LPSC_USB 2
-#define K2HK_LPSC_EMIF25_SPI 3
-#define K2HK_LPSC_TSIP 4
-#define K2HK_LPSC_DEBUGSS_TRC 5
-#define K2HK_LPSC_TETB_TRC 6
-#define K2HK_LPSC_PKTPROC 7
-#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
-#define K2HK_LPSC_SGMII 8
-#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
-#define K2HK_LPSC_CRYPTO 9
-#define K2HK_LPSC_PCIE 10
-#define K2HK_LPSC_SRIO 11
-#define K2HK_LPSC_VUSR0 12
-#define K2HK_LPSC_CHIP_SRSS 13
-#define K2HK_LPSC_MSMC 14
-#define K2HK_LPSC_GEM_0 15
-#define K2HK_LPSC_GEM_1 16
-#define K2HK_LPSC_GEM_2 17
-#define K2HK_LPSC_GEM_3 18
-#define K2HK_LPSC_GEM_4 19
-#define K2HK_LPSC_GEM_5 20
-#define K2HK_LPSC_GEM_6 21
-#define K2HK_LPSC_GEM_7 22
-#define K2HK_LPSC_EMIF4F_DDR3A 23
-#define K2HK_LPSC_EMIF4F_DDR3B 24
-#define K2HK_LPSC_TAC 25
-#define K2HK_LPSC_RAC 26
-#define K2HK_LPSC_RAC_1 27
-#define K2HK_LPSC_FFTC_A 28
-#define K2HK_LPSC_FFTC_B 29
-#define K2HK_LPSC_FFTC_C 30
-#define K2HK_LPSC_FFTC_D 31
-#define K2HK_LPSC_FFTC_E 32
-#define K2HK_LPSC_FFTC_F 33
-#define K2HK_LPSC_AI2 34
-#define K2HK_LPSC_TCP3D_0 35
-#define K2HK_LPSC_TCP3D_1 36
-#define K2HK_LPSC_TCP3D_2 37
-#define K2HK_LPSC_TCP3D_3 38
-#define K2HK_LPSC_VCP2X4_A 39
-#define K2HK_LPSC_CP2X4_B 40
-#define K2HK_LPSC_VCP2X4_C 41
-#define K2HK_LPSC_VCP2X4_D 42
-#define K2HK_LPSC_VCP2X4_E 43
-#define K2HK_LPSC_VCP2X4_F 44
-#define K2HK_LPSC_VCP2X4_G 45
-#define K2HK_LPSC_VCP2X4_H 46
-#define K2HK_LPSC_BCP 47
-#define K2HK_LPSC_DXB 48
-#define K2HK_LPSC_VUSR1 49
-#define K2HK_LPSC_XGE 50
-#define K2HK_LPSC_ARM_SREFLEX 51
-#define K2HK_LPSC_TETRIS 52
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DUMMY1 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE 10
+#define KS2_LPSC_SRIO 11
+#define KS2_LPSC_VUSR0 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_GEM_4 19
+#define KS2_LPSC_GEM_5 20
+#define KS2_LPSC_GEM_6 21
+#define KS2_LPSC_GEM_7 22
+#define KS2_LPSC_EMIF4F_DDR3A 23
+#define KS2_LPSC_EMIF4F_DDR3B 24
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_RAC_1 27
+#define KS2_LPSC_FFTC_A 28
+#define KS2_LPSC_FFTC_B 29
+#define KS2_LPSC_FFTC_C 30
+#define KS2_LPSC_FFTC_D 31
+#define KS2_LPSC_FFTC_E 32
+#define KS2_LPSC_FFTC_F 33
+#define KS2_LPSC_AI2 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 36
+#define KS2_LPSC_TCP3D_2 37
+#define KS2_LPSC_TCP3D_3 38
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_CP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_VCP2X4_E 43
+#define KS2_LPSC_VCP2X4_F 44
+#define KS2_LPSC_VCP2X4_G 45
+#define KS2_LPSC_VCP2X4_H 46
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DXB 48
+#define KS2_LPSC_VUSR1 49
+#define KS2_LPSC_XGE 50
+#define KS2_LPSC_ARM_SREFLEX 51
-/* DDR3A definitions */
-#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
-#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
-#define K2HK_DDR3A_DDRPHYC 0x02329000
/* DDR3B definitions */
-#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
-#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
-#define K2HK_DDR3B_DDRPHYC 0x02328000
-
-/* Queue manager */
-#define DEVICE_QM_MANAGER_BASE 0x02a02000
-#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
-#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
-#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
-#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
-#define DEVICE_QM_NUM_LINKRAMS 2
-#define DEVICE_QM_NUM_MEMREGIONS 20
-
-#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
-#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
-#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
-#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
-
-#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
-#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
-#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
+#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
+#define KS2_DDR3B_DDRPHYC 0x02328000
-/* MSMC control */
-#define K2HK_MSMC_CTRL_BASE 0x0bc00000
+/* Number of DSP cores */
+#define KS2_NUM_DSPS 8
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index ffdecbfcd6d..ddeb06e7bb7 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,42 +22,6 @@
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
-struct ddr3_phy_config {
- unsigned int pllcr;
- unsigned int pgcr1_mask;
- unsigned int pgcr1_val;
- unsigned int ptr0;
- unsigned int ptr1;
- unsigned int ptr2;
- unsigned int ptr3;
- unsigned int ptr4;
- unsigned int dcr_mask;
- unsigned int dcr_val;
- unsigned int dtpr0;
- unsigned int dtpr1;
- unsigned int dtpr2;
- unsigned int mr0;
- unsigned int mr1;
- unsigned int mr2;
- unsigned int dtcr;
- unsigned int pgcr2;
- unsigned int zq0cr1;
- unsigned int zq1cr1;
- unsigned int zq2cr1;
- unsigned int pir_v1;
- unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
- unsigned int sdcfg;
- unsigned int sdtim1;
- unsigned int sdtim2;
- unsigned int sdtim3;
- unsigned int sdtim4;
- unsigned int zqcfg;
- unsigned int sdrfc;
-};
-
#endif
#define BIT(x) (1 << (x))
@@ -105,6 +69,11 @@ struct ddr3_emif_config {
#define NOSRA_MASK 0x08000000
#define ECC_MASK 0x00000001
+/* DDR3 definitions */
+#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
+#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
+#define KS2_DDR3A_DDRPHYC 0x02329000
+
#define KS2_DDR3_MIDR_OFFSET 0x00
#define KS2_DDR3_STATUS_OFFSET 0x04
#define KS2_DDR3_SDCFG_OFFSET 0x08
@@ -116,39 +85,103 @@ struct ddr3_emif_config {
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
+
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
+/* Boot Config */
+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
+#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+/* PSC */
+#define KS2_PSC_BASE 0x02350000
+#define KS2_LPSC_GEM_0 15
+#define KS2_LPSC_TETRIS 52
+#define KS2_TETRIS_PWR_DOMAIN 31
+
+/* Chip configuration unlock codes and registers */
+#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KS2_KICK0_MAGIC 0x83e70b13
+#define KS2_KICK1_MAGIC 0x95a4f1e0
+
+/* PLL control registers */
+#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+#define KS2_PLL_CNTRL_BASE 0x02310000
+#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
+#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
+#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY 0x5a69
+#define KS2_RSTCTRL_MASK 0xffff0000
+#define KS2_RSTCTRL_SWRST 0xfffe0000
+
+/* SPI */
+#define KS2_SPI0_BASE 0x21000400
+#define KS2_SPI1_BASE 0x21000600
+#define KS2_SPI2_BASE 0x21000800
+#define KS2_SPI_BASE KS2_SPI0_BASE
+
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
+/* Flag from ks2_debug options to check if DSPs need to stay ON */
+#define DBG_LEAVE_DSPS_ON 0x1
+
+/* Queue manager */
+#define KS2_QM_MANAGER_BASE 0x02a02000
+#define KS2_QM_DESC_SETUP_BASE 0x02a03000
+#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
+#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
+
+/* MSMC control */
+#define KS2_MSMC_CTRL_BASE 0x0bc00000
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/hardware-k2e.h>
+#endif
+
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
- unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb981) ? 1 : 0;
}
+static inline int cpu_is_k2e(void)
+{
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb9a6) ? 1 : 0;
+}
+
static inline int cpu_revision(void)
{
- unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int rev = (jtag_id >> 28) & 0xf;
return rev;
}
-void share_all_segments(int priv_id);
int cpu_to_bus(u32 *ptr, u32 length);
-void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-void init_ddr3(void);
void sdelay(unsigned long);
#endif
diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h
new file mode 100644
index 00000000000..33a28764bc9
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/mon.h
@@ -0,0 +1,15 @@
+/*
+ * K2HK: secure kernel command header file
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MON_H_
+#define _MON_H_
+
+int mon_power_off(int core_id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
new file mode 100644
index 00000000000..c320db5b65c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/msmc.h
@@ -0,0 +1,17 @@
+/*
+ * MSMC controller
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MSMC_H_
+#define _MSMC_H_
+
+#include <asm/arch/hardware.h>
+
+void msmc_share_all_segments(int priv_id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 4d06ef83fee..53cc2b098a0 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -98,7 +98,6 @@ struct ctrl_id {
#define DEBUG_BASE 0x08000000 /* debug board */
#define NAND_BASE 0x30000000 /* NAND addr */
/* (actual size small port) */
-#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
#define ONENAND_MAP 0x20000000 /* OneNand addr */
/* (actual size small port) */
/* SMS */
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index d2dfb1e19aa..0b78c1ca60f 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -427,20 +427,7 @@ enum {
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
-#define PISMO1_NOR 1
-#define PISMO1_NAND 2
-#define PISMO2_CS0 3
-#define PISMO2_CS1 4
-#define PISMO1_ONENAND 5
#define DBG_MPDB 6
-#define PISMO2_NAND_CS0 7
-#define PISMO2_NAND_CS1 8
-
-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE FLASH_BASE
-#define PISMO1_NAND_BASE NAND_BASE
-#define PISMO2_CS0_BASE PISMO2_MAP1
-#define PISMO1_ONEN_BASE ONENAND_MAP
#define DBG_MPDB_BASE DEBUG_BASE
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d1344ee94c3..183823404d5 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -595,6 +595,14 @@ static inline u32 omap_revision(void)
return *omap_si_rev;
}
+#define OMAP44xx 0x44000000
+
+static inline u8 is_omap44xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFF000000) == OMAP44xx;
+};
+
#define OMAP54xx 0x54000000
static inline u8 is_omap54xx(void)