Merge git://git.denx.de/u-boot-dm

7 files changed, 117 insertions, 4 deletions

diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
new file mode 100644
index 0000000000..5adfd9bca2
--- /dev/null
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -0,0 +1,14 @@
+#include <config.h>
+
+/ {
+	binman {
+		filename = "u-boot-sunxi-with-spl.bin";
+		pad-byte = <0xff>;
+		blob {
+			filename = "spl/sunxi-spl.bin";
+		};
+		u-boot-img {
+			pos = <CONFIG_SPL_PAD_TO>;
+		};
+	};
+};
diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
new file mode 100644
index 0000000000..fff1d78169
--- /dev/null
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	host1x@50000000 {
+		u-boot,dm-pre-reloc;
+		dc@54200000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts
index 3758395c6f..62f89d0f1a 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -27,9 +27,7 @@
 	};
 
 	host1x@50000000 {
-		u-boot,dm-pre-reloc;
 		dc@54200000 {
-			u-boot,dm-pre-reloc;
 			display-timings {
 				timing@0 {
 					clock-frequency = <69500000>;
diff --git a/arch/arm/dts/tegra20-u-boot.dtsi b/arch/arm/dts/tegra20-u-boot.dtsi
new file mode 100644
index 0000000000..9b9835da7e
--- /dev/null
+++ b/arch/arm/dts/tegra20-u-boot.dtsi
@@ -0,0 +1,8 @@
+/ {
+	host1x@50000000 {
+		u-boot,dm-pre-reloc;
+		dc@54200000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 84bb1b0215..e21ee258b3 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -10,7 +10,6 @@
 	interrupt-parent = <&lic>;
 
 	host1x@50000000 {
-		u-boot,dm-pre-reloc;
 		compatible = "nvidia,tegra20-host1x", "simple-bus";
 		reg = <0x50000000 0x00024000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -78,7 +77,6 @@
 		};
 
 		dc@54200000 {
-			u-boot,dm-pre-reloc;
 			compatible = "nvidia,tegra20-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/x86/dts/emulation-u-boot.dtsi b/arch/x86/dts/emulation-u-boot.dtsi
new file mode 100644
index 0000000000..56d34af927
--- /dev/null
+++ b/arch/x86/dts/emulation-u-boot.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <u-boot.dtsi>
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+	binman {
+		u-boot-with-ucode-ptr {
+			optional-ucode;
+		};
+	};
+};
+#endif
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
new file mode 100644
index 0000000000..724913f619
--- /dev/null
+++ b/arch/x86/dts/u-boot.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_ROM_SIZE
+/ {
+	binman {
+		filename = "u-boot.rom";
+		end-at-4gb;
+		sort-by-pos;
+		pad-byte = <0xff>;
+		size = <CONFIG_ROM_SIZE>;
+#ifdef CONFIG_HAVE_INTEL_ME
+		intel-descriptor {
+		};
+		intel-me {
+		};
+#endif
+		u-boot-with-ucode-ptr {
+			pos = <CONFIG_SYS_TEXT_BASE>;
+		};
+		u-boot-dtb-with-ucode {
+		};
+		u-boot-ucode {
+			align = <16>;
+		};
+#ifdef CONFIG_HAVE_MRC
+		intel-mrc {
+			pos = <CONFIG_X86_MRC_ADDR>;
+		};
+#endif
+#ifdef CONFIG_HAVE_FSP
+		intel-fsp {
+			pos = <CONFIG_FSP_ADDR>;
+		};
+#endif
+#ifdef CONFIG_HAVE_CMC
+		intel-cmc {
+			pos = <CONFIG_CMC_ADDR>;
+		};
+#endif
+#ifdef CONFIG_HAVE_VGA_BIOS
+		intel-vga {
+			pos = <CONFIG_VGA_BIOS_ADDR>;
+		};
+#endif
+#ifdef CONFIG_HAVE_REFCODE
+		intel-refcode {
+			pos = <CONFIG_X86_REFCODE_ADDR>;
+		};
+#endif
+		x86-start16 {
+			pos = <CONFIG_SYS_X86_START16>;
+		};
+	};
+};
+#endif