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authorDavid Wu <david.wu@rock-chips.com>2017-09-20 14:37:50 +0800
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2017-10-01 00:33:30 +0200
commit615514c16dee4d43bd584ea326a5a56ebcb89c85 (patch)
treec9a66b0378ef68ef7f9273b4598d0143cb7d5a1c /arch
parentb375d84135e26d5ec5034a515af4df5981785f37 (diff)
rockchip: clk: Add rk3368 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3368.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 2b1197fd46..5f6a5fbe4c 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -89,6 +89,11 @@ enum {
MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK = GENMASK(4, 0),
+ /* CLKSEL_CON25 */
+ CLK_SARADC_DIV_CON_SHIFT = 8,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ CLK_SARADC_DIV_CON_WIDTH = 8,
+
/* CLKSEL43_CON */
GMAC_MUX_SEL_EXTCLK = BIT(8),