Add GPIO parsing on coreboot+uboot combo

BUG=chrome-os-partner:3912
TEST=run vboot_twostop and see cros_gpio output

Change-Id: Ic926765afa5b7d56ed475dc4c9e39a0dc99bcdf0
Reviewed-on: http://gerrit.chromium.org/gerrit/5292
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>

3 files changed, 38 insertions, 1 deletions

diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 3f2281adba..0ffe3a52cd 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -104,6 +104,18 @@ static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
 	info->cmos_checksum_location = cmos_cksum->location;
 }
 
+static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
+{
+	int i;
+	struct cb_gpios *gpios = (struct cb_gpios *)ptr;
+
+	info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ?
+				(gpios->count) : SYSINFO_MAX_GPIOS;
+
+	for (i = 0; i < info->num_gpios; i++)
+		info->gpios[i] = gpios->gpios[i];
+}
+
 static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
 {
 	info->framebuffer = (struct cb_framebuffer *)ptr;
@@ -195,10 +207,12 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 			cb_parse_string(ptr, &info->assembler);
 			break;
 		// FIXME we should warn on serial if coreboot set up a
-		// framebuffer buf the payload does not know about it.
+		// framebuffer but the payload does not know about it.
 		case CB_TAG_FRAMEBUFFER:
 			cb_parse_framebuffer(ptr, info);
 			break;
+		case CB_TAG_GPIO:
+			cb_parse_gpios(ptr, info);
 		}
 
 		ptr += rec->size;
diff --git a/arch/x86/include/asm/ic/coreboot/sysinfo.h b/arch/x86/include/asm/ic/coreboot/sysinfo.h
index 956ced4560..86caaa339d 100644
--- a/arch/x86/include/asm/ic/coreboot/sysinfo.h
+++ b/arch/x86/include/asm/ic/coreboot/sysinfo.h
@@ -31,9 +31,12 @@
 #define _COREBOOT_SYSINFO_H
 
 #include <compiler.h>
+#include <asm/ic/coreboot/tables.h>
 
 /* Allow a maximum of 16 memory range definitions. */
 #define SYSINFO_MAX_MEM_RANGES 16
+/* Allow a maximum of 8 GPIOs */
+#define SYSINFO_MAX_GPIOS 8
 
 struct sysinfo_t {
 	unsigned int cpu_khz;
@@ -68,6 +71,9 @@ struct sysinfo_t {
 
 	struct cb_framebuffer *framebuffer;
 
+	int num_gpios;
+	struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
+
 	unsigned long *mbtable; /** Pointer to the multiboot table */
 };
 
diff --git a/arch/x86/include/asm/ic/coreboot/tables.h b/arch/x86/include/asm/ic/coreboot/tables.h
index a9b76c9808..e9a0c7ba96 100644
--- a/arch/x86/include/asm/ic/coreboot/tables.h
+++ b/arch/x86/include/asm/ic/coreboot/tables.h
@@ -164,6 +164,23 @@ struct cb_framebuffer {
 	u8 reserved_mask_size;
 };
 
+#define CB_TAG_GPIO 0x0013
+#define GPIO_MAX_NAME_LENGTH 16
+struct cb_gpio {
+	u32 port;
+	u32 polarity;
+	u32 value;
+	u8 name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct cb_gpios {
+	u32 tag;
+	u32 size;
+
+	u32 count;
+	struct cb_gpio gpios[0];
+};
+
 #define CB_TAG_CMOS_OPTION_TABLE 0x00c8
 struct cb_cmos_option_table {
 	u32 tag;