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| author | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2015-02-14 01:05:18 +0300 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2015-02-25 13:53:37 +0900 |
| commit | 2cbb17c0e941db629ff2d363c7fef69e47fb7d92 (patch) | |
| tree | 3c07f99e7c1b252c0eca29d6a34da9712b008517 /arch | |
| parent | 89f99a62c1a50d1bad75de315c454c9cf56b2d8d (diff) | |
serial: sh: fix internal clock source on SCIF
The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:
BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0
Also SCSCR must be set to use internal or external clock source.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions