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authorAlison Wang <b18965@freescale.com>2014-12-09 17:38:23 +0800
committerYork Sun <yorksun@freescale.com>2015-01-23 22:29:14 -0600
commit0f5e5579f2b75053e5f05bcba890f7ab2409b460 (patch)
tree6ffa4fe667580e96a89ccee7279ee0bc541e1495 /arch
parentdda3b610eee9dcd433627202584ded417327dd51 (diff)
ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 697d4ca489..afdccdc537 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -105,6 +105,8 @@ struct ccsr_gur {
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
#define SCFG_QSPI_CLKSEL 0xc0100000