tegra: Correct GPIO definitions for Tegra2

The GPIO definitions for Tegra2 were incorrectly matched up with Tegra2.
The layout is actually different, so GPIOs beyond port D do not work.

This separates out the GPIO headers again, so that Tegra2 and Tegra3 have
separate structure definitions.

BUG=None
TEST='vboot_test gpio' on Kaen; see that it responds to google rec, power, lid
correctly

Change-Id: I8540a87c8faa7179c8f0d44ef3f18b3c576392cc
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/9847
Reviewed-by: Bryan Freed <bfreed@chromium.org>
Tested-by: Bryan Freed <bfreed@chromium.org>

3 files changed, 49 insertions, 28 deletions

diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index 1a1e445145..a20574db17 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -30,32 +30,6 @@
 #define GPIO_PORT8(x)	((x) >> 3)
 #define GPIO_BIT(x)	((x) & 0x7)
 
-/* GPIO Controller registers for a single bank */
-struct gpio_ctlr_bank {
-	uint gpio_config[TEGRA_GPIO_PORTS];
-	uint gpio_dir_out[TEGRA_GPIO_PORTS];
-	uint gpio_out[TEGRA_GPIO_PORTS];
-	uint gpio_in[TEGRA_GPIO_PORTS];
-	uint gpio_int_status[TEGRA_GPIO_PORTS];
-	uint gpio_int_enable[TEGRA_GPIO_PORTS];
-	uint gpio_int_level[TEGRA_GPIO_PORTS];
-	uint gpio_int_clear[TEGRA_GPIO_PORTS];
-
-	/* Tegra3 fields */
-	uint gpio_masked_config[TEGRA_GPIO_PORTS];
-	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
-	uint gpio_masked_out[TEGRA_GPIO_PORTS];
-	uint gpio_masked_in[TEGRA_GPIO_PORTS];
-	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
-	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
-	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
-	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
-};
-
-struct gpio_ctlr {
-	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
-};
-
 #define GPIO_PA0    0		/* port A (0), pin 0 */
 #define GPIO_PA1    1
 #define GPIO_PA2    2
diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h
index 6078270df0..00d543550c 100644
--- a/arch/arm/include/asm/arch-tegra2/gpio.h
+++ b/arch/arm/include/asm/arch-tegra2/gpio.h
@@ -24,6 +24,27 @@
 
 #define CONFIG_TEGRA_MAX_GPIO_PORT	27
 
-#include "asm/arch-tegra/gpio.h"
+#include <asm/arch-tegra/gpio.h>
+
+/*
+ * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
 
 #endif	/* TEGRA2_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra3/gpio.h b/arch/arm/include/asm/arch-tegra3/gpio.h
index 4febdcf12d..4035b6bd30 100644
--- a/arch/arm/include/asm/arch-tegra3/gpio.h
+++ b/arch/arm/include/asm/arch-tegra3/gpio.h
@@ -24,11 +24,37 @@
 
 #define CONFIG_TEGRA_MAX_GPIO_PORT	30	/* GPIO_PEEx */
 
+#include <asm/arch-tegra/gpio.h>
+
 /*
  * The Tegra 3x GPIO controller has 246 GPIOs arranged in 8 banks of 4 ports,
  * each with 8 GPIOs.
  */
-#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
 
 #define GPIO_PCC0   224
 #define GPIO_PCC1   225