diff options
| author | Ye Li <ye.li@nxp.com> | 2018-11-07 00:06:06 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-11-08 21:50:48 -0800 |
| commit | f0d02f2da5e475d1e91e92aac3e6a573926fe10a (patch) | |
| tree | 7c000b1cdef1c3681776360a2cae06a468f4fd9b /arch | |
| parent | 81b804a981e1bc78138783e6822bacf88947d039 (diff) | |
MLK-20262 imx8: Disable USDHC clock before setting its parent
According to SCFW API requirement, when setting the clock parent,
the clock must be disabled. Otherwise it will return ERR_BUSY.
When using SPL booting on iMX8QXP, both SPL and regular u-boot will
init the USDHC clock. So the second one in regular u-boot will fail
if we don't disable the clock before setting the parent.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx8/clock.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index f7947fb247a..fb9df7fedcd 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -307,6 +307,13 @@ void init_clk_usdhc(u32 index) if (index >= instances) return; + /* Must disable the clock before set clock parent */ + err = sc_pm_clock_enable(ipc, usdhcs[index], SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) { + printf("SDHC_%d per clk enable failed!\n", index); + return; + } + /* * IMX8QXP USDHC_CLK_ROOT default source from DPLL, but this DPLL * do not stable, will cause usdhc data transfer crc error. So here |