diff options
| author | Ye Li <ye.li@nxp.com> | 2019-10-25 01:28:48 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-10-27 20:11:40 -0700 |
| commit | 70af44d36f9c28d24dce88447a4ad8eaaae5c441 (patch) | |
| tree | 28417939190b40355fdfba3afcb3c1f83a9aa2af /arch | |
| parent | 7209491b7f0295663b7a3ce3c01371d8ce0f340f (diff) | |
MLK-22851-3 imx8mq: Enable eMMC HS400 and SD UHS mode on EVK
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.
The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us
to SD reset pin, otherwise some SD cards will fail to select UHS mode in
re-initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-imx8mq-evk.dts | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mq.c | 6 |
2 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts index 6b713f98c0..252d6f8ab8 100644 --- a/arch/arm/dts/fsl-imx8mq-evk.dts +++ b/arch/arm/dts/fsl-imx8mq-evk.dts @@ -46,6 +46,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; }; diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 33a4d51f9c..a55786f063 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -462,15 +462,13 @@ void init_clk_usdhc(u32 index) case 0: clock_enable(CCGR_USDHC1, 0); clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC1, 1); return; case 1: clock_enable(CCGR_USDHC2, 0); clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC2, 1); return; default: |