Merge branch 'master' of git://git.denx.de/u-boot-sunxi

14 files changed, 228 insertions, 474 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 69f852012e..790571b773 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -382,6 +382,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-orangepi-prime.dtb \
 	sun50i-h5-orangepi-zero-plus2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
+	sun50i-a64-amarula-relic.dtb \
 	sun50i-a64-bananapi-m64.dtb \
 	sun50i-a64-nanopi-a64.dtb \
 	sun50i-a64-olinuxino.dtb \
diff --git a/arch/arm/dts/sun50i-a64-amarula-relic.dts b/arch/arm/dts/sun50i-a64-amarula-relic.dts
new file mode 100644
index 0000000000..f3b4e93ece
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-amarula-relic.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Amarula A64-Relic";
+	compatible = "amarula,a64-relic", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
index 02db114113..dcde4a4881 100644
--- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts
@@ -68,6 +68,14 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
@@ -108,6 +116,14 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
@@ -119,3 +135,13 @@
 	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
 	status = "okay";
 };
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+	status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
index d1c347d2b8..a65300d5aa 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -50,6 +50,11 @@
 	model = "OrangePi PC 2";
 	compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
 
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@@ -58,11 +63,6 @@
 		reg = <0x40000000 0x40000000>;
 	};
 
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &emac;
-	};
-
 	soc {
 		reg_vcc3v3: vcc3v3 {
 			compatible = "regulator-fixed";
@@ -73,6 +73,29 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	status = "okay";
+};
+
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
 &mmc0 {
 	compatible = "allwinner,sun50i-h5-mmc",
 		     "allwinner,sun50i-a64-mmc",
@@ -86,13 +109,7 @@
 	status = "okay";
 };
 
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&usbphy {
+&ohci0 {
 	status = "okay";
 };
 
@@ -100,21 +117,17 @@
 	status = "okay";
 };
 
-&ehci1 {
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
 	status = "okay";
 };
 
-&emac {
-	pinctrl-names = "default";
-	pinctrl-0 = <&emac_rgmii_pins>;
-	phy-mode = "rgmii";
-	phy-handle = <&ext_rgmii_phy>;
+&usb_otg {
+	dr_mode = "otg";
 	status = "okay";
 };
 
-&external_mdio {
-	ext_rgmii_phy: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
+&usbphy {
+	status = "okay";
 };
diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts
index d4577dfae1..131d8058c4 100644
--- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts
@@ -72,6 +72,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -89,6 +93,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };
@@ -99,6 +107,11 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
 	status = "okay";
 };
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
index bab6c1812b..2953e0fdac 100644
--- a/arch/arm/dts/sun8i-a83t.dtsi
+++ b/arch/arm/dts/sun8i-a83t.dtsi
@@ -230,13 +230,29 @@
 			reg = <0x01c19000 0x400>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
+		usbphy: phy@1c19400 {
+			compatible = "allwinner,sun8i-a83t-usb-phy";
+			reg = <0x01c19400 0x10>,
+			      <0x01c1a800 0x14>,
+			      <0x01c1b800 0x14>;
+			reg-names = "phy_ctrl",
+				    "pmu1",
+				    "pmu2";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
 		ehci0: usb@01c1a000 {
 			compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
 			reg = <0x01c1a000 0x100>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
@@ -244,6 +260,8 @@
 			compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci";
 			reg = <0x01c1a400 0x100>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
@@ -251,6 +269,8 @@
 			compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
index f3b1d5f6db..e766aa3e2f 100644
--- a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -93,6 +93,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -146,6 +150,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };
@@ -189,6 +197,11 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
 	/* USB VBUS is on as long as VCC-IO is on */
 	status = "okay";
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index d9d31fa3f5..1df6ca4f31 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -219,6 +219,19 @@
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb@1c19000 {
+			compatible = "allwinner,sun8i-h3-musb";
+			reg = <0x01c19000 0x400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
 		usbphy: phy@01c19400 {
 			compatible = "allwinner,sun8i-h3-usb-phy";
 			reg = <0x01c19400 0x2c>,
@@ -251,6 +264,25 @@
 			#phy-cells = <1>;
 		};
 
+		ehci0: usb@1c1a000 {
+			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+			reg = <0x01c1a000 0x100>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb@1c1a400 {
+			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+			reg = <0x01c1a400 0x100>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
 		ehci1: usb@01c1b000 {
 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 72e95afd78..5adfd9bca2 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -1,14 +1,5 @@
 #include <config.h>
 
-/*
- * This is the maximum size the U-Boot binary can be, which is basically
- * the start of the environment, minus the start of the U-Boot binary in
- * the MMC. This makes the assumption that the MMC is using 512-bytes
- * blocks, but devices using something other than that remains to be
- * seen.
- */
-#define UBOOT_MMC_MAX_SIZE	(CONFIG_ENV_OFFSET - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512))
-
 / {
 	binman {
 		filename = "u-boot-sunxi-with-spl.bin";
@@ -17,9 +8,6 @@
 			filename = "spl/sunxi-spl.bin";
 		};
 		u-boot-img {
-#ifdef CONFIG_MMC
-			size = <UBOOT_MMC_MAX_SIZE>;
-#endif
 			pos = <CONFIG_SPL_PAD_TO>;
 		};
 	};
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 27a0da938c..8acf79fbba 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -270,21 +270,27 @@ struct sunxi_ccm_reg {
 #define AXI_GATE_OFFSET_DRAM		0
 
 /* ahb_gate0 offsets */
-#define AHB_GATE_OFFSET_USB_OHCI1	30
-#define AHB_GATE_OFFSET_USB_OHCI0	29
 #ifdef CONFIG_MACH_SUNXI_H3_H5
 /*
  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
  */
+#define AHB_GATE_OFFSET_USB_OHCI0	28
 #define AHB_GATE_OFFSET_USB_EHCI2	27
 #define AHB_GATE_OFFSET_USB_EHCI1	26
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#elif defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI0	29
 #define AHB_GATE_OFFSET_USB_EHCI0	25
 #else
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
-#ifndef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN50I
+#define AHB_GATE_OFFSET_USB0		23
+#elif !defined(CONFIG_MACH_SUN8I_R40)
 #define AHB_GATE_OFFSET_USB0		24
 #else
 #define AHB_GATE_OFFSET_USB0		25
@@ -344,13 +350,10 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
 #else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h
deleted file mode 100644
index 39e7af45dd..0000000000
--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Sunxi usb-phy code
- *
- * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
- * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- */
-
-int sunxi_usb_phy_probe(void);
-int sunxi_usb_phy_remove(void);
-void sunxi_usb_phy_init(int index);
-void sunxi_usb_phy_exit(int index);
-void sunxi_usb_phy_power_on(int index);
-void sunxi_usb_phy_power_off(int index);
-int sunxi_usb_phy_vbus_detect(int index);
-int sunxi_usb_phy_id_detect(int index);
-void sunxi_usb_phy_enable_squelch_detect(int index, int enable);
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index f0c9d1b058..a3f7723028 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -124,6 +124,7 @@ endif
 config MACH_SUNXI_H3_H5
 	bool
 	select DM_I2C
+	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_32BIT
@@ -138,6 +139,7 @@ config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
+	select PHY_SUN4I_USB
 	select DRAM_SUN4I
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
@@ -147,6 +149,7 @@ config MACH_SUN5I
 	select CPU_V7A
 	select ARM_CORTEX_CPU_IS_UP
 	select DRAM_SUN4I
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	imply CONS_INDEX_2 if !DM_SERIAL
@@ -158,6 +161,7 @@ config MACH_SUN6I
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN6I
+	select PHY_SUN4I_USB
 	select SUN6I_P2WI
 	select SUN6I_PRCM
 	select SUNXI_GEN_SUN6I
@@ -171,6 +175,7 @@ config MACH_SUN7I
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN4I
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -182,6 +187,7 @@ config MACH_SUN8I_A23
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A23
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -194,6 +200,7 @@ config MACH_SUN8I_A33
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
 	select DRAM_SUN8I_A33
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -203,6 +210,7 @@ config MACH_SUN8I_A83T
 	bool "sun8i (Allwinner A83T)"
 	select CPU_V7A
 	select DRAM_SUN8I_A83T
+	select PHY_SUN4I_USB
 	select SUNXI_GEN_SUN6I
 	select MMC_SUNXI_HAS_NEW_MODE
 	select SUPPORT_SPL
@@ -253,6 +261,7 @@ config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
 	select DM_I2C
+	select PHY_SUN4I_USB
 	select SUNXI_DE2
 	select SUNXI_GEN_SUN6I
 	select SUNXI_HIGH_SRAM
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 1e261bdc87..4c752491a1 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -11,9 +11,6 @@ obj-y	+= clock.o
 obj-y	+= cpu_info.o
 obj-y	+= dram_helpers.o
 obj-y	+= pinmux.o
-ifndef CONFIG_MACH_SUN9I
-obj-y	+= usb_phy.o
-endif
 obj-$(CONFIG_SUN6I_P2WI)	+= p2wi.o
 obj-$(CONFIG_SUN6I_PRCM)	+= prcm.o
 obj-$(CONFIG_AXP_PMIC_BUS)	+= pmic_bus.o
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
deleted file mode 100644
index 318e225528..0000000000
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ /dev/null
@@ -1,406 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Sunxi usb-phy code
- *
- * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
- * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/usb_phy.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <errno.h>
-
-#if defined(CONFIG_MACH_SUN4I) ||		   \
-	defined(CONFIG_MACH_SUN5I) ||		   \
-	defined(CONFIG_MACH_SUN6I) ||		   \
-	defined(CONFIG_MACH_SUN7I) ||		   \
-	defined(CONFIG_MACH_SUN8I_A23) ||	   \
-	defined(CONFIG_MACH_SUN9I)
-#define SUNXI_USB_CSR			0x404
-#else
-#define SUNXI_USB_CSR			0x410
-#endif
-
-#define SUNXI_USB_PMU_IRQ_ENABLE	0x800
-#define SUNXI_USB_PASSBY_EN		1
-
-#define SUNXI_EHCI_AHB_ICHR8_EN		(1 << 10)
-#define SUNXI_EHCI_AHB_INCR4_BURST_EN	(1 << 9)
-#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN	(1 << 8)
-#define SUNXI_EHCI_ULPI_BYPASS_EN	(1 << 0)
-
-#define REG_PHY_UNK_H3			0x420
-#define REG_PMU_UNK_H3			0x810
-
-/* A83T specific control bits for PHY0 */
-#define SUNXI_PHY_CTL_VBUSVLDEXT	BIT(5)
-#define SUNXI_PHY_CTL_SIDDQ		BIT(3)
-
-/* A83T HSIC specific bits */
-#define SUNXI_EHCI_HS_FORCE		BIT(20)
-#define SUNXI_EHCI_CONNECT_DET		BIT(17)
-#define SUNXI_EHCI_CONNECT_INT		BIT(16)
-#define SUNXI_EHCI_HSIC			BIT(1)
-
-static struct sunxi_usb_phy {
-	int usb_rst_mask;
-	int gpio_vbus;
-	int gpio_vbus_det;
-	int gpio_id_det;
-	int id;
-	int init_count;
-	int power_on_count;
-	ulong base;
-} sunxi_usb_phy[] = {
-	{
-		.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
-		.id = 0,
-		.base = SUNXI_USB0_BASE,
-	},
-	{
-		.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
-		.id = 1,
-		.base = SUNXI_USB1_BASE,
-	},
-#if CONFIG_SUNXI_USB_PHYS >= 3
-	{
-#ifdef CONFIG_MACH_SUN8I_A83T
-		.usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
-				CCM_USB_CTRL_12M_CLK,
-#else
-		.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
-#endif
-		.id = 2,
-		.base = SUNXI_USB2_BASE,
-	},
-#endif
-#if CONFIG_SUNXI_USB_PHYS >= 4
-	{
-		.usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
-		.id = 3,
-		.base = SUNXI_USB3_BASE,
-	}
-#endif
-};
-
-static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
-
-static int get_vbus_gpio(int index)
-{
-	switch (index) {
-	case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
-	case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
-	case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
-	case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
-	}
-	return -EINVAL;
-}
-
-static int get_vbus_detect_gpio(int index)
-{
-	switch (index) {
-	case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
-	}
-	return -EINVAL;
-}
-
-static int get_id_detect_gpio(int index)
-{
-	switch (index) {
-	case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
-	}
-	return -EINVAL;
-}
-
-__maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
-					 int data, int len)
-{
-	int j = 0, usbc_bit = 0;
-	void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
-
-#ifdef CONFIG_MACH_SUN8I_A33
-	/* CSR needs to be explicitly initialized to 0 on A33 */
-	writel(0, dest);
-#endif
-
-	usbc_bit = 1 << (phy->id * 2);
-	for (j = 0; j < len; j++) {
-		/* set the bit address to be written */
-		clrbits_le32(dest, 0xff << 8);
-		setbits_le32(dest, (addr + j) << 8);
-
-		clrbits_le32(dest, usbc_bit);
-		/* set data bit */
-		if (data & 0x1)
-			setbits_le32(dest, 1 << 7);
-		else
-			clrbits_le32(dest, 1 << 7);
-
-		setbits_le32(dest, usbc_bit);
-
-		clrbits_le32(dest, usbc_bit);
-
-		data >>= 1;
-	}
-}
-
-#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
-static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
-{
-#if defined CONFIG_MACH_SUNXI_H3_H5
-	if (phy->id == 0)
-		clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
-#endif
-	clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
-}
-#elif defined CONFIG_MACH_SUN8I_A83T
-static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
-{
-}
-#else
-static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
-{
-	/* The following comments are machine
-	 * translated from Chinese, you have been warned!
-	 */
-
-	/* Regulation 45 ohms */
-	if (phy->id == 0)
-		usb_phy_write(phy, 0x0c, 0x01, 1);
-
-	/* adjust PHY's magnitude and rate */
-	usb_phy_write(phy, 0x20, 0x14, 5);
-
-	/* threshold adjustment disconnect */
-#if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
-	usb_phy_write(phy, 0x2a, 2, 2);
-#else
-	usb_phy_write(phy, 0x2a, 3, 2);
-#endif
-
-	return;
-}
-#endif
-
-static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
-{
-	unsigned long bits = 0;
-	void *addr;
-
-	addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
-
-	bits = SUNXI_EHCI_AHB_ICHR8_EN |
-		SUNXI_EHCI_AHB_INCR4_BURST_EN |
-		SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
-		SUNXI_EHCI_ULPI_BYPASS_EN;
-
-#ifdef CONFIG_MACH_SUN8I_A83T
-	if (phy->id == 2)
-		bits |= SUNXI_EHCI_HS_FORCE |
-			SUNXI_EHCI_CONNECT_INT |
-			SUNXI_EHCI_HSIC;
-#endif
-
-	if (enable)
-		setbits_le32(addr, bits);
-	else
-		clrbits_le32(addr, bits);
-
-	return;
-}
-
-void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
-{
-#ifndef CONFIG_MACH_SUN8I_A83T
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
-	usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
-#endif
-}
-
-void sunxi_usb_phy_init(int index)
-{
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-	phy->init_count++;
-	if (phy->init_count != 1)
-		return;
-
-	setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
-
-	sunxi_usb_phy_config(phy);
-
-	if (phy->id != 0)
-		sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
-
-#ifdef CONFIG_MACH_SUN8I_A83T
-	if (phy->id == 0) {
-		setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
-			     SUNXI_PHY_CTL_VBUSVLDEXT);
-		clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
-			     SUNXI_PHY_CTL_SIDDQ);
-	}
-#endif
-}
-
-void sunxi_usb_phy_exit(int index)
-{
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-	phy->init_count--;
-	if (phy->init_count != 0)
-		return;
-
-	if (phy->id != 0)
-		sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
-
-#ifdef CONFIG_MACH_SUN8I_A83T
-	if (phy->id == 0) {
-		setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
-			     SUNXI_PHY_CTL_SIDDQ);
-	}
-#endif
-
-	clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
-}
-
-void sunxi_usb_phy_power_on(int index)
-{
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
-	if (initial_usb_scan_delay) {
-		mdelay(initial_usb_scan_delay);
-		initial_usb_scan_delay = 0;
-	}
-
-	phy->power_on_count++;
-	if (phy->power_on_count != 1)
-		return;
-
-	if (phy->gpio_vbus >= 0)
-		gpio_set_value(phy->gpio_vbus, 1);
-}
-
-void sunxi_usb_phy_power_off(int index)
-{
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
-	phy->power_on_count--;
-	if (phy->power_on_count != 0)
-		return;
-
-	if (phy->gpio_vbus >= 0)
-		gpio_set_value(phy->gpio_vbus, 0);
-}
-
-int sunxi_usb_phy_vbus_detect(int index)
-{
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-	int err, retries = 3;
-
-	if (phy->gpio_vbus_det < 0)
-		return phy->gpio_vbus_det;
-
-	err = gpio_get_value(phy->gpio_vbus_det);
-	/*
-	 * Vbus may have been provided by the board and just been turned of
-	 * some milliseconds ago on reset, what we're measuring then is a
-	 * residual charge on Vbus, sleep a bit and try again.
-	 */
-	while (err > 0 && retries--) {
-		mdelay(100);
-		err = gpio_get_value(phy->gpio_vbus_det);
-	}
-
-	return err;
-}
-
-int sunxi_usb_phy_id_detect(int index)
-{
-	struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
-
-	if (phy->gpio_id_det < 0)
-		return phy->gpio_id_det;
-
-	return gpio_get_value(phy->gpio_id_det);
-}
-
-int sunxi_usb_phy_probe(void)
-{
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	struct sunxi_usb_phy *phy;
-	int i, ret = 0;
-
-	for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
-		phy = &sunxi_usb_phy[i];
-
-		phy->gpio_vbus = get_vbus_gpio(i);
-		if (phy->gpio_vbus >= 0) {
-			ret = gpio_request(phy->gpio_vbus, "usb_vbus");
-			if (ret)
-				return ret;
-			ret = gpio_direction_output(phy->gpio_vbus, 0);
-			if (ret)
-				return ret;
-		}
-
-		phy->gpio_vbus_det = get_vbus_detect_gpio(i);
-		if (phy->gpio_vbus_det >= 0) {
-			ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
-			if (ret)
-				return ret;
-			ret = gpio_direction_input(phy->gpio_vbus_det);
-			if (ret)
-				return ret;
-		}
-
-		phy->gpio_id_det = get_id_detect_gpio(i);
-		if (phy->gpio_id_det >= 0) {
-			ret = gpio_request(phy->gpio_id_det, "usb_id_det");
-			if (ret)
-				return ret;
-			ret = gpio_direction_input(phy->gpio_id_det);
-			if (ret)
-				return ret;
-			sunxi_gpio_set_pull(phy->gpio_id_det,
-					    SUNXI_GPIO_PULL_UP);
-		}
-	}
-
-	setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
-	return 0;
-}
-
-int sunxi_usb_phy_remove(void)
-{
-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	struct sunxi_usb_phy *phy;
-	int i;
-
-	clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
-	for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
-		phy = &sunxi_usb_phy[i];
-
-		if (phy->gpio_vbus >= 0)
-			gpio_free(phy->gpio_vbus);
-
-		if (phy->gpio_vbus_det >= 0)
-			gpio_free(phy->gpio_vbus_det);
-
-		if (phy->gpio_id_det >= 0)
-			gpio_free(phy->gpio_id_det);
-	}
-
-	return 0;
-}