diff options
| author | Nikhil Badola <nikhil.badola@freescale.com> | 2015-06-26 16:59:21 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-08-03 12:06:38 -0700 |
| commit | ca7fb12cc18e80d14cca9570aec1d544f5d8c169 (patch) | |
| tree | 931afc9c2b8d3d0ced54f34ff4d4831b8e46c117 /arch | |
| parent | 56848428a88f89420ae7acc04bb5805e70c430a3 (diff) | |
armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 8675e91fca..032cfd80eb 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,7 @@ #include <fsl_ddrc_version.h> #define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 |