tegra: Move tegra_get_chip_type() to ap20.c

This function is better off in architecture code than board code.
This is quite an invasive change unfortunately.

BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I17764b134c25b684666d2c0fae2d255ac80e61b1
Reviewed-on: https://gerrit.chromium.org/gerrit/12244
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>

4 files changed, 56 insertions, 5 deletions

diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c
index 787b3e4b3b..913d8aaa77 100644
--- a/arch/arm/cpu/armv7/tegra-common/ap20.c
+++ b/arch/arm/cpu/armv7/tegra-common/ap20.c
@@ -23,18 +23,18 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap20.h>
 #include <asm/arch-tegra/bitfield.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/flow.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/i2c.h>
 #include <asm/arch-tegra/pmc.h>
-#include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/scu.h>
-#include <asm/arch-tegra/i2c.h>
 #include <asm/arch-tegra/warmboot.h>
-#include <asm/arch-tegra/ap20.h>
-#include "../../../../../board/nvidia/common/board.h"
 
 struct clk_pll_table {
 	u16		n;
@@ -94,6 +94,39 @@ enum tegra_family_t {
 
 #define GP_HIDREV	0x804
 
+int tegra_get_chip_type(void)
+{
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
+	uint tegra_sku_id;
+
+	tegra_sku_id = readl(&fuse->sku_info) & 0xff;
+
+	switch (tegra_sku_id) {
+	case SKU_ID_T20:
+		return TEGRA_SOC_T20;
+	case SKU_ID_T25SE:
+	case SKU_ID_AP25:
+	case SKU_ID_T25:
+	case SKU_ID_AP25E:
+	case SKU_ID_T25E:
+		return TEGRA_SOC_T25;
+	case SKU_ID_T30:
+		/*
+		 * T30 has two options. We will return TEGRA_SOC_T30 until
+		 * we have the fdt set up when it may change to
+		 * TEGRA_SOC_T30_408MHZ depending on what we set PLLP to.
+		 */
+		if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000)
+			return TEGRA_SOC_T30_408MHZ;
+		else
+			return TEGRA_SOC_T30;
+
+	default:
+		/* unknown sku id */
+		return TEGRA_SOC_UNKNOWN;
+	}
+}
+
 static enum tegra_family_t ap20_get_family(void)
 {
 	u32 reg, chip_id;
diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c
index 65f74fcbc4..1334df21c7 100644
--- a/arch/arm/cpu/armv7/tegra-common/clock.c
+++ b/arch/arm/cpu/armv7/tegra-common/clock.c
@@ -1398,4 +1398,5 @@ void clock_init(void)
 	debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
 	debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
 	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
+	debug("Chip type = %d\n", tegra_get_chip_type());
 }
diff --git a/arch/arm/include/asm/arch-tegra/ap20.h b/arch/arm/include/asm/arch-tegra/ap20.h
index 0bc239977b..6c1e57eea3 100644
--- a/arch/arm/include/asm/arch-tegra/ap20.h
+++ b/arch/arm/include/asm/arch-tegra/ap20.h
@@ -118,3 +118,14 @@ void ap20_init_pllx(int slow);
  * @return number of CPUs (1-4)
  */
 int ap20_get_num_cpus(void);
+
+/**
+ * Works out the SOC type used for clocks settings
+ *
+ * Note that T30 will return TEGRA_SOC_T30 until we have the fdt set up,
+ * when it may change to TEGRA_SOC_T30_408MHZ depending on what we set PLLP
+ * to.
+ *
+ * @return	SOC type - see TEGRA_SOC...
+ */
+int tegra_get_chip_type(void);
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 3820918c04..b7119c00b0 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -89,6 +89,12 @@ enum {
 	SKU_ID_T30		= 0x81,	/* TBD use real Cardhu value */
 };
 
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
 enum {
 	TEGRA_SOC_T20,
 	TEGRA_SOC_T25,