diff options
author | Ye Li <ye.li@nxp.com> | 2020-04-30 00:46:41 -0700 |
---|---|---|
committer | Ye Li <ye.li@nxp.com> | 2020-04-30 01:55:55 -0700 |
commit | c251cbece893b9206301218ecc81242e2b5b2c0b (patch) | |
tree | 9f6534fa7672c0807baa7b6c07ecf628a664937f /arch | |
parent | aafacf1b5f1bf6fcb290d094500f5473b5eedf60 (diff) |
MLK-23574-46 imx8qxp: Add iMX8QXP/iMX8DX validation board support
Add the validation board support for iMX8QXP/iMX8DX platforms.
- iMX8QXP 21x21 DDR3 board
- iMX8QXP 21x21 LPDDR4 board
- iMX8QXP 17x17 LPDDR4 board
- iMX8DX 17x17 DDR3 board
Ready functions: SD/eMMC, flexspi, ENET, USB, i2c and NAND
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/dts/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/dts/fsl-imx8dx-17x17-val.dts | 19 | ||||
-rw-r--r-- | arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi | 101 | ||||
-rw-r--r-- | arch/arm/dts/fsl-imx8qxp-17x17-val.dts | 49 | ||||
-rw-r--r-- | arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts | 52 | ||||
-rw-r--r-- | arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi | 217 | ||||
-rw-r--r-- | arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts | 433 | ||||
-rw-r--r-- | arch/arm/mach-imx/imx8/Kconfig | 16 |
8 files changed, 891 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ee1a38b486..3626b6110e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -735,6 +735,10 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb \ + fsl-imx8qxp-lpddr4-val.dtb \ + fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \ + fsl-imx8qxp-17x17-val.dtb \ + fsl-imx8dx-17x17-val.dtb \ fsl-imx8dx-mek.dtb \ fsl-imx8dxl-phantom-mek.dtb \ fsl-imx8dxl-evk.dtb \ diff --git a/arch/arm/dts/fsl-imx8dx-17x17-val.dts b/arch/arm/dts/fsl-imx8dx-17x17-val.dts new file mode 100644 index 0000000000..970fac337e --- /dev/null +++ b/arch/arm/dts/fsl-imx8dx-17x17-val.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-17x17-val.dts" + +/ { + model = "NXP i.MX8DX 17x17 Validation board"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi new file mode 100644 index 0000000000..c7160f4678 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-val} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val.dts b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts new file mode 100644 index 0000000000..4ee085f9f1 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * + */ + +#include "fsl-imx8qxp-lpddr4-val.dts" + +/ { + model = "NXP i.MX8QXP 17x17 Validation board"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + status = "disabled"; + + /delete-node/ gpio@18; + /delete-node/ gpio@19; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usbotg3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts new file mode 100644 index 0000000000..69004cd615 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +#include "fsl-imx8qxp-lpddr4-val.dts" + +&iomuxc { + imx8qxp-val { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + SC_P_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + SC_P_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + SC_P_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + SC_P_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi new file mode 100644 index 0000000000..8c882aae61 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + +}; + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-val} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts new file mode 100644 index 0000000000..941089bf9f --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "NXP i.MX8QXP LPDDR4 VAL"; + compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp"; + + aliases { + gpio8 = &pca9557_a; + gpio9 = &pca9557_b; + gpio10 = &pca9557_c; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <300>; + off-on-delay-us = <5000>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qxp-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x0600002c + SC_P_UART0_TX_ADMA_UART0_TX 0x0600002c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + it6263-0@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-1@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 87c4ae3029..977030ad41 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -117,6 +117,21 @@ config TARGET_IMX8QXP_MEK select BOARD_LATE_INIT select IMX8QXP +config TARGET_IMX8QXP_LPDDR4_VAL + bool "Support i.MX8QXP lpddr4 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8QXP_DDR3_VAL + bool "Support i.MX8QXP ddr3 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8X_17X17_VAL + bool "Support i.MX8QXP/DX 17x17 validation board" + select BOARD_LATE_INIT + select IMX8QXP + config TARGET_IMX8DXL_PHANTOM_MEK bool "Support i.MX8DXL PHANTOM MEK board" select BOARD_LATE_INIT @@ -143,6 +158,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/freescale/imx8qm_val/Kconfig" +source "board/freescale/imx8qxp_val/Kconfig" source "board/freescale/imx8dxl_phantom_mek/Kconfig" source "board/freescale/imx8dxl_evk/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" |