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authorMichael Walle <michael@walle.cc>2021-04-13 17:54:17 +0200
committerPriyanka Jain <priyanka.jain@nxp.com>2021-06-16 18:14:08 +0530
commit2bf4658b8c5e5f4f43dc1888fe39ea61e6eeba64 (patch)
tree5d7a650fc02ce859b34339005cbd3b3c9ecb78b0 /arch
parentfb4e64ef9daefba6c98e6a9620e28ffee741c075 (diff)
board: sl28: fix RGMII clock and voltage
It was noticed that the clock isn't continuously enabled when there is no link. This is because the 125MHz clock is derived from the internal PLL which seems to go into some kind of power-down mode every once in a while. The LS1028A expects a contiuous clock. Thus enable the PLL all the time. Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO regulator. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts3
-rw-r--r--arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts3
2 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
index fe708bdbfa0..33d85ed83a6 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
@@ -41,8 +41,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+ qca,keep-pll-enabled;
- vddio-supply = <&vddh>;
+ vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
index 33b16303adb..b95e082b70b 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
@@ -32,8 +32,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+ qca,keep-pll-enabled;
- vddio-supply = <&vddh>;
+ vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";