Merge git://git.denx.de/u-boot-fsl-qoriq

5 files changed, 44 insertions, 16 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d08262971e..00d2564c79 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -538,8 +538,8 @@ int arch_early_init_r(void)
 	 * erratum A009635 is valid only for LS2080A SoC and
 	 * its personalitiesi
 	 */
-	svr_dev_id = get_svr() >> 16;
-	if (svr_dev_id == SVR_DEV_LS2080A)
+	svr_dev_id = get_svr();
+	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
 		erratum_a009635();
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
@@ -604,8 +604,8 @@ int timer_init(void)
 	 * For LS2080A SoC and its personalities, timer controller
 	 * offset is different
 	 */
-	svr_dev_id = get_svr() >> 16;
-	if (svr_dev_id == SVR_DEV_LS2080A)
+	svr_dev_id = get_svr();
+	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
 		cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index 025a1b7b2e..6c98d99d0c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
@@ -154,8 +154,8 @@ Booting from NAND
 -------------------
 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
 The difference between NAND boot RCW image and NOR boot image is the PBI
-command sequence. Below is one example for PBI commands for QDS which uses
-NAND device with 2KB/page, block size 128KB.
+command sequence. Below is one example for PBI commands for LS2085AQDS which
+uses NAND device with 2KB/page, block size 128KB.
 
 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
@@ -188,7 +188,7 @@ nand write <u-boot image in memory> 200000 <size of u-boot image>
 
 With these two images in NAND device, the board can boot from NAND.
 
-Another example for RDB boards,
+Another example for LS2085ARDB boards,
 
 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
@@ -201,6 +201,8 @@ nand write <u-boot image in memory> 80000 <size of u-boot image>
 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
 to match board NAND device with 4KB/page, block size 512KB.
 
+Note, LS2088A and LS1088A don't support booting from NAND.
+
 Booting from SD/eMMC
 -------------------
 Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index cae59da803..39ffe1ab4d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
 	int addr_cells;
 	u64 val, core_id;
 	size_t *boot_code_size = &(__secondary_boot_code_size);
+	u32 mask = cpu_pos_mask();
+	int off_prev = -1;
+
+	off = fdt_path_offset(blob, "/cpus");
+	if (off < 0) {
+		puts("couldn't find /cpus node\n");
+		return;
+	}
+
+	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
+
+	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+					    "cpu", 4);
+	while (off != -FDT_ERR_NOTFOUND) {
+		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+		if (reg) {
+			core_id = fdt_read_number(reg, addr_cells);
+			if (!test_bit(id_to_core(core_id), &mask)) {
+				fdt_del_node(blob, off);
+				off = off_prev;
+			}
+		}
+		off_prev = off;
+		off = fdt_node_offset_by_prop_value(blob, off_prev,
+						    "device_type", "cpu", 4);
+	}
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
 	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
 	int node;
@@ -145,7 +172,7 @@ static void fdt_fixup_gic(void *blob)
 
 	val = gur_in32(&gur->svr);
 
-	if (SVR_SOC_VER(val) != SVR_LS1043A) {
+	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
 		align_64k = 1;
 	} else if (SVR_REV(val) != REV1_0) {
 		val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +354,7 @@ static void fdt_fixup_msi(void *blob)
 
 	rev = gur_in32(&gur->svr);
 
-	if (SVR_SOC_VER(rev) != SVR_LS1043A)
+	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
 		return;
 
 	rev = SVR_REV(rev);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index fa93096c68..c089ceef32 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
 	ldr     x2, =DCFG_CCSR_SVR
 	ldr	w2, [x2]
 	rev	w2, w2
-	mov	w3, w2
-	ands	w3, w3, #SVR_WO_E << 8
-	mov	w4, #SVR_LS1043A << 8
+	lsr	w3, w2, #16
+	ldr	w4, =SVR_DEV(SVR_LS1043A)
 	cmp	w3, w4
 	b.ne	1f
 	ands	w2, w2, #0xff
@@ -92,7 +91,7 @@ ENTRY(lowlevel_init)
 	 */
 	bl	get_svr
 	lsr	w0, w0, #16
-	ldr	w1, =SVR_DEV_LS2080A
+	ldr	w1, =SVR_DEV(SVR_LS2080A)
 	cmp	w0, w1
 	b.eq	1f
 
@@ -224,7 +223,7 @@ ENTRY(lowlevel_init)
 	 */
 	bl	get_svr
 	lsr	w0, w0, #16
-	ldr	w1, =SVR_DEV_LS2080A
+	ldr	w1, =SVR_DEV(SVR_LS2080A)
 	cmp	w0, w1
 	b.eq	1f
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..09f64e7bd7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -76,8 +76,6 @@ struct cpu_type {
 #define SVR_LS2081A		0x870918
 #define SVR_LS2041A		0x870914
 
-#define SVR_DEV_LS2080A		0x8701
-
 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
 #define SVR_REV(svr)		(((svr) >> 0) & 0xff)
@@ -85,6 +83,8 @@ struct cpu_type {
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
 		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr)		((svr) >> 8)
+#define IS_SVR_DEV(svr, dev)	(((svr) >> 16) == (dev))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe