summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorMicah Catlin <micahc@chromium.org>2011-11-02 16:44:45 -0700
committerGerrit <chrome-bot@google.com>2011-11-29 11:06:39 -0800
commit03fde2c4e5546902e99409e68bf1d63851328f31 (patch)
tree5f47deb0a501c38e523b897e22f86c758fd81043 /arch
parent515096ad20283ed02cd48788ad65d7272941403f (diff)
Changing implementation of pllx_set_rate() to reduce possibility of intermittent hang
Currently with 200uS delay after PLL for stability. BUG=chrome-os-partner:6145 TEST=None Originaly-Reviewed-on: https://gerrit.chromium.org/gerrit/11091 Originaly-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Originaly-Tested-by: Bernie Thompson <bhthompson@chromium.org> Originaly-Commit-Ready: Katie Roberts-Hoffman <katierh@chromium.org> Originaly-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Change-Id: Idcb95d4698ea856785be8a8232c08c89309af887 Reviewed-on: https://gerrit.chromium.org/gerrit/12158
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/tegra-common/ap20.c27
1 files changed, 18 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c
index 679277b85e2..787b3e4b3bc 100644
--- a/arch/arm/cpu/armv7/tegra-common/ap20.c
+++ b/arch/arm/cpu/armv7/tegra-common/ap20.c
@@ -144,22 +144,31 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp,
{
u32 reg;
- /* Set BYPASS, m, n and p to PLLX_BASE */
- reg = bf_pack(PLL_BYPASS, 1) | bf_pack(PLL_DIVM, divm);
- reg |= bf_pack(PLL_DIVN, divn) | bf_pack(PLL_DIVP, divp);
+ reg = readl(&pll->pll_base);
+ /* Set m, n and p to PLLX_BASE */
+ bf_update(PLL_DIVM, reg, divm);
+ bf_update(PLL_DIVN, reg, divn);
+ bf_update(PLL_DIVP, reg, divp);
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
reg = bf_pack(PLL_CPCON, cpcon);
writel(reg, &pll->pll_misc);
- /* Enable PLLX */
reg = readl(&pll->pll_base);
- reg |= bf_pack(PLL_ENABLE, 1);
-
- /* Disable BYPASS */
- reg &= ~bf_mask(PLL_BYPASS);
- writel(reg, &pll->pll_base);
+ /* Enable PLLX if not enabled */
+ if (!bf_unpack(PLL_ENABLE, reg)) {
+ bf_update(PLL_ENABLE, reg, 1);
+ bf_update(PLL_BYPASS, reg, 0);
+ writel(reg, &pll->pll_base);
+ /*
+ * Wait for 200uS, this is done based on what is done in the
+ * Linux kernel PLL code for Tegra2, this is being kept here
+ * for now pending on going stability testing on removing
+ * or lowering it.
+ */
+ udelay(200);
+ }
return 0;
}