LogicPD Support for OMAP3/DM3/AM3 boards 2.1 Update

5 files changed, 258 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 549ac19189d..598457610f0 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -74,7 +74,11 @@ void dieid_num_r(void)
  ******************************************/
 u32 get_cpu_type(void)
 {
-	return readl(&ctrl_base->ctrl_omap_stat);
+	u32 cpu_type;
+	cpu_type = readl(&ctrl_base->ctrl_omap_stat);
+	if (cpu_type == OMAP3730_WRONG_EFUSE)
+		cpu_type = OMAP3730;
+	return cpu_type;
 }
 
 /******************************************
diff --git a/arch/arm/include/asm/arch-omap3/dma.h b/arch/arm/include/asm/arch-omap3/dma.h
new file mode 100644
index 00000000000..edc2cbf98e7
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/dma.h
@@ -0,0 +1,183 @@
+#ifndef __SDMA_H
+#define __SDMA_H
+
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz <at> corscience.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+// #ifndef __KERNEL_STRICT_NAMES
+// #ifndef __ASSEMBLY__
+struct dma4_chan {
+	u32 ccr;
+	u32 clnk_ctrl;
+	u32 cicr;
+	u32 csr;
+	u32 csdp;
+	u32 cen;
+	u32 cfn;
+	u32 cssa;
+	u32 cdsa;
+	u32 csel;
+	u32 csfl;
+	u32 cdel;
+	u32 cdfl;
+	u32 csac;
+	u32 cdac;
+	u32 ccen;
+	u32 ccfn;
+	u32 color;
+};
+
+struct dma4_chan_padded {
+	u32 ccr;
+	u32 clnk_ctrl;
+	u32 cicr;
+	u32 csr;
+	u32 csdp;
+	u32 cen;
+	u32 cfn;
+	u32 cssa;
+	u32 cdsa;
+	u32 csel;
+	u32 csfl;
+	u32 cdel;
+	u32 cdfl;
+	u32 csac;
+	u32 cdac;
+	u32 ccen;
+	u32 ccfn;
+	u32 color;
+	u8 res1[0x60 - sizeof(struct dma4_chan)];
+};
+
+struct dma4 {
+	u32 revision;
+	u8 res1[0x4];
+	u32 irqstatus_l[0x4];
+	u32 irqenable_l[0x4];
+	u32 sysstatus;
+	u32 ocp_sysconfig;
+	u8 res2[0x34];
+	u32 caps_0;
+	u8 res3[0x4];
+	u32 caps_2;
+	u32 caps_3;
+	u32 caps_4;
+	u32 gcr;
+	u8 res4[0x4];
+	/* Dinon - Use dma4_chan_padded instead of dma4_chan for
+	 * channel 1 ~ 31 to work */
+	struct dma4_chan_padded chan[32];
+};
+// #endif /*__ASSEMBLY__ */
+// #endif /* __KERNEL_STRICT_NAMES */
+
+/* Functions */
+void omap3_dma_init(void);
+int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
+		uint32_t sze);
+int omap3_dma_start_transfer(uint32_t chan);
+int omap3_dma_wait_for_transfer(uint32_t chan, int chained);
+int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
+int omap3_dma_set_conf_chan(uint32_t chan, struct dma4_chan *config);
+int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
+int omap3_dma_transfer(int channel, void *src, void *dst, int size, int flags);
+void omap3_dma_channel_init(int channel, int next_channel, int csdp_size,
+			int ccr_src_amode, int ccr_dst_amode);
+
+#define DMA_CHANNEL_NAND		0
+#define DMA_CHANNEL_MMC			1
+
+/* Register settings */
+#define CSDP_DATA_TYPE_8BIT             0x0
+#define CSDP_DATA_TYPE_16BIT            0x1
+#define CSDP_DATA_TYPE_32BIT            0x2
+#define CSDP_SRC_BURST_SINGLE           (0x0 << 7)
+#define CSDP_SRC_BURST_EN_16BYTES       (0x1 << 7)
+#define CSDP_SRC_BURST_EN_32BYTES       (0x2 << 7)
+#define CSDP_SRC_BURST_EN_64BYTES       (0x3 << 7)
+#define CSDP_DST_BURST_SINGLE           (0x0 << 14)
+#define CSDP_DST_BURST_EN_16BYTES       (0x1 << 14)
+#define CSDP_DST_BURST_EN_32BYTES       (0x2 << 14)
+#define CSDP_DST_BURST_EN_64BYTES       (0x3 << 14)
+#define CSDP_DST_ENDIAN_LOCK_ADAPT      (0x0 << 18)
+#define CSDP_DST_ENDIAN_LOCK_LOCK       (0x1 << 18)
+#define CSDP_DST_ENDIAN_LITTLE          (0x0 << 19)
+#define CSDP_DST_ENDIAN_BIG             (0x1 << 19)
+#define CSDP_SRC_ENDIAN_LOCK_ADAPT      (0x0 << 20)
+#define CSDP_SRC_ENDIAN_LOCK_LOCK       (0x1 << 20)
+#define CSDP_SRC_ENDIAN_LITTLE          (0x0 << 21)
+#define CSDP_SRC_ENDIAN_BIG             (0x1 << 21)
+
+#define CICR_MISALIGNED_ERR_IE		(0x1 << 11)
+#define CICR_SUPERVISOR_ERR_IE		(0x1 << 10)
+#define CICR_TRANS_ERR_IE		(0x1 << 8)
+#define CICR_BLOCK_IE			(0x1 << 5)
+
+#define CCR_READ_PRIORITY_LOW           (0x0 << 6)
+#define CCR_READ_PRIORITY_HIGH          (0x1 << 6)
+#define CCR_ENABLE_DISABLED             (0x0 << 7)
+#define CCR_ENABLE_ENABLE               (0x1 << 7)
+#define CCR_SRC_AMODE_CONSTANT          (0x0 << 12)
+#define CCR_SRC_AMODE_POST_INC          (0x1 << 12)
+#define CCR_SRC_AMODE_SINGLE_IDX        (0x2 << 12)
+#define CCR_SRC_AMODE_DOUBLE_IDX        (0x3 << 12)
+#define CCR_DST_AMODE_CONSTANT          (0x0 << 14)
+#define CCR_DST_AMODE_POST_INC          (0x1 << 14)
+#define CCR_DST_AMODE_SINGLE_IDX        (0x2 << 14)
+#define CCR_DST_AMODE_SOUBLE_IDX        (0x3 << 14)
+
+#define CCR_RD_ACTIVE_MASK              (1 << 9)
+#define CCR_WR_ACTIVE_MASK              (1 << 10)
+
+#define CSR_SUPER_BLOCK			(0x1 << 14)
+#define CSR_DRAIN_END			(0x1 << 12)
+#define CSR_MISALIGNED_ADRS_ERR		(0x1 << 11)
+#define CSR_SUPERVISOR_ERR		(0x1 << 10)
+#define CSR_TRANS_ERR			(0x1 << 8)
+#define CSR_PKT				(0x1 << 7)
+#define CSR_SYNC			(0x1 << 6)
+#define CSR_BLOCK			(0x1 << 5)
+#define CSR_LAST			(0x1 << 4)
+#define CSR_FRAME			(0x1 << 3)
+#define CSR_HALF			(0x1 << 2)
+#define CSR_DROP			(0x1 << 1)
+
+#if 1
+#define CSR_ALL_MASK	\
+	(CSR_MISALIGNED_ADRS_ERR \
+	| CSR_SUPERVISOR_ERR | CSR_TRANS_ERR | CSR_PKT | CSR_SYNC \
+	| CSR_BLOCK | CSR_LAST | CSR_FRAME | CSR_HALF | CSR_DROP)
+#else
+#define CSR_ALL_MASK	\
+	(CSR_SUPER_BLOCK | CSR_DRAIN_END | CSR_MISALIGNED_ADRS_ERR \
+	| CSR_SUPERVISOR_ERR | CSR_TRANS_ERR | CSR_PKT | CSR_SYNC \
+	| CSR_BLOCK | CSR_LAST | CSR_FRAME | CSR_HALF | CSR_DROP)
+#endif
+
+#define CLNK_CTRL_ENABLE_LNK		(1 << 15)
+
+/* others */
+#define CHAN_NR_MIN			0
+#define CHAN_NR_MAX			31
+
+
+#define FB_DMA_START			(1 << 0)
+#define FB_DMA_WAIT			(1 << 1)
+
+#endif /* __SDMA_H */
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 8c91b9aac9f..117ad1ee611 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -47,6 +47,8 @@
 #define OMAP34XX_L4_PER			0x49000000
 #define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
 
+#define OMAP34XX_DMA4_BASE		0x48056000
+
 /* CONTROL */
 #define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE + 0x2000)
 
@@ -248,5 +250,6 @@ struct gpio {
 #define AM3517			0x1c00
 
 #define OMAP3730		0x0c00
+#define OMAP3730_WRONG_EFUSE	0x0e00
 
 #endif
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 2e223199471..21e6feb182c 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -50,6 +50,7 @@
 #include <asm/arch/sys_proto.h>
 #include <onenand_uboot.h>
 #include <mmc.h>
+#include <asm/arch/dma.h>
 
 #ifdef CONFIG_BITBANGMII
 #include <miiphy.h>
@@ -465,6 +466,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
+#if defined(CONFIG_OMAP_DMA)
+	omap3_dma_init();
+#endif
+
 #ifdef CONFIG_LOGBUFFER
 	logbuff_init_ptrs ();
 #endif
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 30686fe69b7..80a8205a2c2 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -25,6 +25,68 @@
 
 #include <common.h>
 
+#ifdef CONFIG_OMAP34XX
+/* Cache routine for OMAP34XX (Cortex-A8) */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	unsigned int cache_level_id;		/* cache level ID register */
+	unsigned int cache_size_id;	/* cache size ID register */
+	unsigned long addr, end_addr;
+	unsigned int level;
+	unsigned int line_size;
+	unsigned int assoc, num_sets;
+
+	/* First get the cache ID register */
+	asm("mrc p15, 1, %0, c0, c0, 1 @ get cache level ID" : "=r" (cache_level_id) : : "cc");
+	/* Strip off LoU/LoC */
+	cache_level_id &= ~0xFF000000;
+
+	/* Loop over the levels until there's no higher order cache */
+	for (level = 0; cache_level_id; level+=2) {
+		/* Select the level */
+		asm volatile("mcr p15, 2, %0, c0, c0, 0 @ Select cache level"
+			: : "r" (level) : "cc");
+
+		asm("mrc p15, 1, %0, c0, c0, 0 @ get cache size ID" : "=r" (cache_size_id) : : "cc");
+
+		/* Number of bytes in line */
+		line_size = (1 << ((cache_size_id & 0x3) + 2)) * 4;
+
+		/* Calculate number of sets * associativity to
+		 * figure if its easier to use MVA vs set/way */
+		assoc = ((cache_size_id >> 2) + 1) & 0x3ff;
+		num_sets = ((cache_size_id >> 13) + 1) & 0x7fff;
+
+		if (0 && (assoc * num_sets * line_size) > (stop - start)) {
+			/* Cheaper to flush/invalidate using set/way */
+			;
+		} else {
+			/* Cheaper to flush/invalidate using MVA */
+			addr = start & ~line_size;
+			end_addr = (stop + line_size - 1) & ~line_size;
+
+			/* Clean and invalidate each line */
+			for (; addr < end_addr; addr += line_size) {
+				asm volatile("mcr p15, 0, %0, c7, c14, 1 @ clean/invalidate Dcache" : : "r" (addr) : "cc");
+			}
+		}
+
+		/* Peel off this cache layer and continue until no more */
+		cache_level_id >>= 3;
+	}
+
+	/* Switch back to level 0 */
+	asm volatile("mcr p15, 2, %0, c0, c0, 0 @ Cache Size SelectID"
+		: : "r" (0) : "cc");
+
+	asm volatile("mcr p15, 0, %0, c7, c5, 4	@ flush prefetch buffer" : : "r" (0) : "cc");
+#if 0
+	/* invalidate the I-cache */
+	asm volatile("mcr p15 0, %0, c7, c5, 0 @ I+BTB cache invalidate", : : "r" (0) : "cc");
+#endif
+}
+#endif
+
 void  flush_cache (unsigned long dummy1, unsigned long dummy2)
 {
 #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)