Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05

- Fix mkimage recognition
- Update all my fragments

ZynqMP:
- Use clk driver
- Support loading elfs in el1
- Various DTS and defconfig changes
- Enable newer pmufw versions
- Support more clocks
- Remove ep108
- Secure image support
- Fix memtest setup

Zynq:
- Enabling watchdog driver
- Support more clocks
- defconfig changes

fpga:
- Simplify error path

net:
- GMII case update

13 files changed, 304 insertions, 414 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b8f7a982d9c..068ea1e8776 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -762,6 +762,7 @@ config ARCH_ZYNQ
 	select SUPPORT_SPL
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
+	select BOARD_EARLY_INIT_F if WDT
 	select SPL_OF_CONTROL if SPL
 	select DM
 	select DM_ETH if NET
@@ -1359,6 +1360,7 @@ source "board/toradex/colibri_pxa270/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/zynqmp/Kconfig"
 source "board/zipitz2/Kconfig"
 
 source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index bc77dd03c36..14e7d400649 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -185,7 +185,7 @@ void zynqmp_pmufw_version(void)
 	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 
-	if (pm_api_version != ZYNQMP_PM_VERSION)
+	if (pm_api_version < ZYNQMP_PM_VERSION)
 		panic("PMUFW version error. Expected: v%d.%d\n",
 		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7dd1dffae59..e983622fea5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -146,7 +146,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zturn-myir.dtb \
 	zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
-	zynqmp-ep108.dtb			\
 	zynqmp-mini-emmc.dtb			\
 	zynqmp-mini-nand.dtb			\
 	zynqmp-zcu102-revA.dtb			\
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index d342306293b..a88a83c1665 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -333,3 +333,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usb0_default>;
 };
+
+&watchdog0 {
+	reset-on-timeout;
+};
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
new file mode 100644
index 00000000000..4449d5b93d1
--- /dev/null
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -0,0 +1,290 @@
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	fclk0: fclk0 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 71>;
+	};
+
+	fclk1: fclk1 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 72>;
+	};
+
+	fclk2: fclk2 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 73>;
+	};
+
+	fclk3: fclk3 {
+		status = "disabled";
+		compatible = "xlnx,fclk";
+		clocks = <&clkc 74>;
+	};
+
+	pss_ref_clk: pss_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <33333333>;
+	};
+
+	video_clk: video_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
+	pss_alt_ref_clk: pss_alt_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	gt_crx_ref_clk: gt_crx_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <108000000>;
+	};
+
+	aux_ref_clk: aux_ref_clk {
+		u-boot,dm-pre-reloc;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
+	clkc: clkc {
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		compatible = "xlnx,zynqmp-clkc";
+		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
+		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
+		clock-output-names = "iopll", "rpll", "apll", "dpll",
+				"vpll", "iopll_to_fpd", "rpll_to_fpd",
+				"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
+				"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
+				"dbg_trace", "dbg_tstmp", "dp_video_ref",
+				"dp_audio_ref", "dp_stc_ref", "gdma_ref",
+				"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
+				"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
+				"topsw_main", "topsw_lsbus", "gtgref0_ref",
+				"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
+				"usb1_bus_ref", "usb3_dual_ref", "usb0",
+				"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
+				"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
+				"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
+				"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
+				"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
+				"uart0_ref", "uart1_ref", "spi0_ref",
+				"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
+				"can0_ref", "can1_ref", "can0", "can1",
+				"dll_ref", "adma_ref", "timestamp_ref",
+				"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
+	};
+
+	dp_aclk: dp_aclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-accuracy = <100>;
+	};
+};
+
+&can0 {
+	clocks = <&clkc 63>, <&clkc 31>;
+};
+
+&can1 {
+	clocks = <&clkc 64>, <&clkc 31>;
+};
+
+&cpu0 {
+	clocks = <&clkc 10>;
+};
+
+&fpd_dma_chan1 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan2 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan3 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan4 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan5 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan6 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan7 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&fpd_dma_chan8 {
+	clocks = <&clkc 19>, <&clkc 31>;
+};
+
+&gpu {
+	clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
+};
+
+&lpd_dma_chan1 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan2 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan3 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan4 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan5 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan6 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan7 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&lpd_dma_chan8 {
+	clocks = <&clkc 68>, <&clkc 31>;
+};
+
+&nand0 {
+	clocks = <&clkc 60>, <&clkc 31>;
+};
+
+&gem0 {
+	clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem1 {
+	clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem2 {
+	clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem3 {
+	clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
+	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gpio {
+	clocks = <&clkc 31>;
+};
+
+&i2c0 {
+	clocks = <&clkc 61>;
+};
+
+&i2c1 {
+	clocks = <&clkc 62>;
+};
+
+&pcie {
+	clocks = <&clkc 23>;
+};
+
+&qspi {
+	clocks = <&clkc 53>, <&clkc 31>;
+};
+
+&sata {
+	clocks = <&clkc 22>;
+};
+
+&sdhci0 {
+	clocks = <&clkc 54>, <&clkc 31>;
+};
+
+&sdhci1 {
+	clocks = <&clkc 55>, <&clkc 31>;
+};
+
+&spi0 {
+	clocks = <&clkc 58>, <&clkc 31>;
+};
+
+&spi1 {
+	clocks = <&clkc 59>, <&clkc 31>;
+};
+
+&uart0 {
+	clocks = <&clkc 56>,  <&clkc 31>;
+};
+
+&uart1 {
+	clocks = <&clkc 57>,  <&clkc 31>;
+};
+
+&usb0 {
+	clocks = <&clkc 32>,  <&clkc 34>;
+};
+
+&usb1 {
+	clocks = <&clkc 33>,  <&clkc 34>;
+};
+
+&watchdog0 {
+	clocks = <&clkc 75>;
+};
+
+&xilinx_ams {
+	clocks = <&clkc 70>;
+};
+
+&xilinx_drm {
+	clocks = <&clkc 16>;
+};
+
+&xlnx_dp {
+	clocks = <&dp_aclk>, <&clkc 17>;
+};
+
+&xlnx_dpdma {
+	clocks = <&clkc 20>;
+};
+
+&xlnx_dp_snd_codec0 {
+	clocks = <&clkc 17>;
+};
diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
deleted file mode 100644
index 12d9fe14988..00000000000
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * clock specification for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/ {
-	misc_clk: misc_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-		u-boot,dm-pre-reloc;
-	};
-
-	i2c_clk: i2c_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0x0>;
-		clock-frequency = <111111111>;
-	};
-
-	sata_clk: sata_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <75000000>;
-	};
-
-	dp_aclk: clock0 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <50000000>;
-		clock-accuracy = <100>;
-	};
-
-	clk100: clk100 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
-	clk600: clk600 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <600000000>;
-	};
-
-	dp_aud_clk: clock1 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <22579200>;
-		clock-accuracy = <100>;
-	};
-};
-
-&can0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&can1 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&fpd_dma_chan1 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan2 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan3 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan4 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan5 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan6 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan7 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan8 {
-	clocks = <&clk600>, <&clk100>;
-};
-
-&gem0 {
-	clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
-};
-
-&gpio {
-	clocks = <&misc_clk>;
-};
-
-&i2c0 {
-	clocks = <&i2c_clk>;
-};
-
-&i2c1 {
-	clocks = <&i2c_clk>;
-};
-
-&nand0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&qspi {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&sata {
-	clocks = <&sata_clk>;
-};
-
-&sdhci0 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&sdhci1 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&spi0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&spi1 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&uart0 {
-	clocks = <&misc_clk &misc_clk>;
-};
-
-&usb0 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&usb1 {
-	clocks = <&misc_clk>, <&misc_clk>;
-};
-
-&watchdog0 {
-	clocks= <&misc_clk>;
-};
-
-&xilinx_drm {
-	clocks = <&misc_clk>;
-};
-
-&xlnx_dp {
-	clocks = <&dp_aclk>, <&dp_aud_clk>;
-};
-
-&xlnx_dp_snd_codec0 {
-	clocks = <&dp_aud_clk>;
-};
-
-&xlnx_dpdma {
-	clocks = <&misc_clk>;
-};
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
deleted file mode 100644
index a16ffdc3f0c..00000000000
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * dts file for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-ep108-clk.dtsi"
-
-/ {
-	model = "ZynqMP EP108";
-
-	aliases {
-		ethernet0 = &gem0;
-		mmc0 = &sdhci0;
-		mmc1 = &sdhci1;
-		serial0 = &uart0;
-		spi0 = &qspi;
-		spi1 = &spi0;
-		spi2 = &spi1;
-		usb0 = &usb0;
-		usb1 = &usb1;
-	};
-
-	chosen {
-		bootargs = "earlycon";
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x40000000>;
-	};
-};
-
-&can0 {
-	status = "okay";
-};
-
-&can1 {
-	status = "okay";
-};
-
-&gem0 {
-	status = "okay";
-	phy-handle = <&phy0>;
-	phy-mode = "rgmii-id";
-	phy0: phy@0 {
-		reg = <0>;
-		max-speed = <100>;
-	};
-};
-
-&gpio {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <400000>;
-	eeprom@54 {
-		compatible = "atmel,24c64";
-		reg = <0x54>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-	clock-frequency = <400000>;
-	eeprom@55 {
-		compatible = "atmel,24c64";
-		reg = <0x55>;
-	};
-};
-
-&nand0 {
-	status = "okay";
-	arasan,has-mdma;
-	num-cs = <1>;
-
-	partition@0 {	/* for testing purpose */
-		label = "nand-fsbl-uboot";
-		reg = <0x0 0x0 0x400000>;
-	};
-	partition@1 {	/* for testing purpose */
-		label = "nand-linux";
-		reg = <0x0 0x400000 0x1400000>;
-	};
-	partition@2 {	/* for testing purpose */
-		label = "nand-device-tree";
-		reg = <0x0 0x1800000 0x400000>;
-	};
-	partition@3 {	/* for testing purpose */
-		label = "nand-rootfs";
-		reg = <0x0 0x1C00000 0x1400000>;
-	};
-	partition@4 {	/* for testing purpose */
-		label = "nand-bitstream";
-		reg = <0x0 0x3000000 0x400000>;
-	};
-	partition@5 {	/* for testing purpose */
-		label = "nand-misc";
-		reg = <0x0 0x3400000 0xFCC00000>;
-	};
-};
-
-&qspi {
-	status = "okay";
-	flash@0 {
-		compatible = "m25p80";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <10000000>;
-		partition@qspi-fsbl-uboot { /* for testing purpose */
-			label = "qspi-fsbl-uboot";
-			reg = <0x0 0x100000>;
-		};
-		partition@qspi-linux { /* for testing purpose */
-			label = "qspi-linux";
-			reg = <0x100000 0x500000>;
-		};
-		partition@qspi-device-tree { /* for testing purpose */
-			label = "qspi-device-tree";
-			reg = <0x600000 0x20000>;
-		};
-		partition@qspi-rootfs { /* for testing purpose */
-			label = "qspi-rootfs";
-			reg = <0x620000 0x5E0000>;
-		};
-	};
-};
-
-&sata {
-	status = "okay";
-	ceva,broken-gen2;
-	/* SATA Phy OOB timing settings */
-	ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
-	ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
-	ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
-	ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
-	ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
-	ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
-	ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
-	ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
-};
-
-&sdhci0 {
-	status = "okay";
-	bus-width = <8>;
-	xlnx,mio_bank = <2>;
-};
-
-&sdhci1 {
-	status = "okay";
-	xlnx,mio_bank = <1>;
-};
-
-&spi0 {
-	status = "okay";
-	num-cs = <1>;
-	spi0_flash0: spi0_flash0@0 {
-		compatible = "m25p80";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-
-		spi0_flash0@0 {
-			label = "spi0_flash0";
-			reg = <0x0 0x100000>;
-		};
-	};
-};
-
-&spi1 {
-	status = "okay";
-	num-cs = <1>;
-	spi1_flash0: spi1_flash0@0 {
-		compatible = "m25p80";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-
-		spi1_flash0@0 {
-			label = "spi1_flash0";
-			reg = <0x0 0x100000>;
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&dwc3_0 {
-	status = "okay";
-	dr_mode = "peripheral";
-	maximum-speed = "high-speed";
-};
-
-&usb1 {
-	status = "okay";
-};
-
-&dwc3_1 {
-	status = "okay";
-	dr_mode = "host";
-	maximum-speed = "high-speed";
-};
-
-&watchdog0 {
-	status = "okay";
-};
-
-&xlnx_dp {
-	xlnx,max-pclock-frequency = <200000>;
-};
-
-&xlnx_dpdma {
-	xlnx,axi-clock-freq = <200000000>;
-};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 04d82c4d2ec..9062ffe919e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
 	model = "ZynqMP zc1751-xm015-dc1 RevA";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 7dfe960135a..bf43bf87488 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
 	model = "ZynqMP zc1751-xm016-dc2 RevA";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 648e3ba7993..39c82c592f7 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
 	model = "ZynqMP zc1751-xm018-dc4";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index f3020a57600..c774b866fb1 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -12,7 +12,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 / {
 	model = "ZynqMP zc1751-xm019-dc5 RevA";
 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 64a883b96e3..2be6eb0eb5e 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -11,7 +11,7 @@
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 #include <dt-bindings/phy/phy.h>
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 084d55a2b01..ad3dc9aba50 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -11,6 +11,8 @@
 #define PAYLOAD_ARG_CNT		5
 
 #define ZYNQMP_CSU_SILICON_VER_MASK	0xF
+#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD	0xC200002D
+#define KEY_PTR_LEN	32
 
 enum {
 	IDCODE,