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authorSimon Glass <sjg@chromium.org>2016-09-25 21:33:24 -0600
committerBin Meng <bmeng.cn@gmail.com>2016-10-11 11:55:33 +0800
commitd30b3103a56b5340f85dfadfb6ef52626700ee67 (patch)
tree5366390946d25b05a07e73edc879200dcbfc1300 /arch/x86
parent35233da98a53eb95a28d16d3fd836801b84015a9 (diff)
x86: Correct address casts in cpu code
We should cast an address to unsigned long, not u32. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/cpu/cpu.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 269043dedc1..7c1d6deda9d 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -135,7 +135,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
struct gdt_ptr gdt;
gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
- gdt.ptr = (u32)boot_gdt;
+ gdt.ptr = (ulong)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
@@ -630,13 +630,11 @@ static void build_pagetable(uint32_t *pgtable)
memset(pgtable, '\0', PAGETABLE_SIZE);
/* Level 4 needs a single entry */
- pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+ pgtable[0] = (ulong)&pgtable[1024] + 7;
/* Level 3 has one 64-bit entry for each GiB of memory */
- for (i = 0; i < 4; i++) {
- pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
- 0x1000 * i + 7;
- }
+ for (i = 0; i < 4; i++)
+ pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
for (i = 0; i < 2048; i++)