diff options
| author | Simon Glass <sjg@chromium.org> | 2016-09-25 21:33:34 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-10-11 11:55:33 +0800 |
| commit | 4e0318c32f01e5178f9ddd29313fcb24a1584dd6 (patch) | |
| tree | 720f51439e05effcf209ef44eef7f1fcded665d6 /arch/x86 | |
| parent | 5d7ec3d8d3f09293824d1486b33cbe578e896996 (diff) | |
x86: ivybridge: Fix PCH power setup
At present pch_power_options() has the arguments to writel() around the
wrong way. Fix this and update it to compile on 64-bit machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/ivybridge/lpc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 4e0be2a88b9..91c9c0e35e8 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -213,10 +213,10 @@ static int pch_power_options(struct udevice *pch) dm_pci_read_config16(pch, 0x40, &pmbase); pmbase &= 0xfffe; - writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, - "intel,gpe0-enable", 0)); - writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node, - "intel,alt-gp-smi-enable", 0)); + writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0), + (ulong)pmbase + GPE0_EN); + writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0), + (ulong)pmbase + ALT_GP_SMI_EN); /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); /* PM1_CNT */ |