diff options
| author | Heinrich Schuchardt <xypron.glpk@gmx.de> | 2020-12-22 07:53:03 +0100 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2021-01-30 14:25:41 -0700 |
| commit | a0df924928906b9da095dcbfa63dd5503e3ac3df (patch) | |
| tree | 8d974d953ed4d592b010334e68dff6b37e8f7317 /arch/x86 | |
| parent | 5c6ba71bbe1285cfd323574dca88b8484a38aecd (diff) | |
x86: typo segement
%s/segement/segment/
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/i386/cpu.c | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/start.S | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 7517b756f43..6fa0f4d32ba 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -175,7 +175,7 @@ void arch_setup_gd(gd_t *new_gd) * Per Intel FSP external architecture specification, before calling any FSP * APIs, we need make sure the system is in flat 32-bit mode and both the code * and data selectors should have full 4GB access range. Here we reuse the one - * we used in arch/x86/cpu/start16.S, and reload the segement registers. + * we used in arch/x86/cpu/start16.S, and reload the segment registers. */ void setup_fsp_gdt(void) { diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 3b6ed37bc07..3d0d95295f6 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -77,7 +77,7 @@ _start: lgdt gdt_ptr2 #endif - /* Load the segement registers to match the GDT loaded in start16.S */ + /* Load the segment registers to match the GDT loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax movw %ax, %fs movw %ax, %ds |