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authorBin Meng <bmeng.cn@gmail.com>2015-09-09 23:20:28 -0700
committerSimon Glass <sjg@chromium.org>2015-09-16 19:53:53 -0600
commit5bf0f7f65d40447cec0f3d91abda59eb4a4f88af (patch)
treeda3aae3084ca4a484534ec3ca15edc98eaf62d1c /arch/x86/dts/galileo.dts
parent554778c240385b09dc01140865fe3f5d04806456 (diff)
x86: galileo: Add PCIe root port IRQ routing
Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/galileo.dts')
-rw-r--r--arch/x86/dts/galileo.dts12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index f119bf7f42..a4e16760d5 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -92,6 +92,18 @@
PCI_BDF(0, 21, 0) INTA PIRQE
PCI_BDF(0, 21, 1) INTB PIRQF
PCI_BDF(0, 21, 2) INTC PIRQG
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 1) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
>;
};
};